Datasheet

CPU Registers
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor 35
Figure 3-2. Stacking Operations
SP-9
STACK
SP-1
ACMLTR A
ACMLTR B
CONDITION CODE
SP-2
SP-3
SP-4
SP-5
SP-6
SP-7
SP-8
INDEX REGISTER (Y
L
)
INDEX REGISTER (Y
H
)
INDEX REGISTER (X
L
)
INDEX REGISTER (X
H
)
RTN
L
RTN
H
STACK
SP-2
SP-1
SP
RTN
L
RTN
H
STACK
SP-2
SP-1
SP
RTN
L
RTN
H
$9D = JSR
dd
NEXT MAIN INSTR
DIRECT
MAIN PROGRAM
$AD = JSR
ff
NEXT MAIN INSTR
INDXD,X
MAIN PROGRAM
PC
RTN
PC
RTN
$18 = PRE
ff
NEXT MAIN INSTR
INDXD,Y
MAIN PROGRAM
PC
RTN
$AD = JSR
$BD = JSR
ll
NEXT MAIN INSTR
EXTEND
MAIN PROGRAM
PC
RTN
hh
$8D = BSR
rr
NEXT MAIN INSTR
MAIN PROGRAM
$39 = RTS
SUBROUTINE
PC
RTN
PC
BSR, BRANCH TO SUBROUTINE
STACK
SP
SP+1
SP+2
RTS, RETURN FROM SUBROUTINE
$3F = SWI
MAIN PROGRAM
PC
SWI, SOFTWARE INTERRUPT
RTN
$3E = WAI
MAIN PROGRAM
PC
WAI, WAIT FOR INTERRUPT
RTN
$3B = RTI
INTERRUPT PROGRAM
PC
STACK
SP+1
SP
RTI, RETURN FROM INTERRUPT
ACMLTR A
ACMLTR B
CONDITION CODE
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
LEGEND:
RTN
RTN
H
RTN
L
dd
ff
hh
ll
rr
Address of next instruction in main program to be
executed upon return from subroutine
Most significant byte of return address
Least significant byte of return address
8-bit direct address ($0000–$00FF) (high byte
assumed to be $00).
8-bit positive offset $00 (0) to $FF (256) is added
to index.
High-order byte of 16-bit extended address.
Low-order byte of 16-bit extended address.
Signed-relative offset $80 (–128) to $7F (+127)
(offset relative to the address following the
machine code offset byte).
JSR, JUMP TO SUBROUTINE
Shaded cells show stack pointer position after
operation is complete.
RTN
L
RTN
H
INDEX REGISTER (Y
L
)
INDEX REGISTER (Y
H
)
INDEX REGISTER (X
L
)
INDEX REGISTER (X
H
)
RTN
L
RTN
H
SP
$6E = JMP
ff
MAIN PROGRAM
NEXT INSTRUCTION
INDXD,X
PC
X + ff
$18 = PRE
ff
MAIN PROGRAM
PC
$6E = JMP
JMP, JUMP
NEXT INSTRUCTIONX + ff
INDXD,Y
$7E = JMP
ll
MAIN PROGRAM
PC
hh
NEXT INSTRUCTIONhh ll
EXTND