Datasheet

MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor 33
Chapter 3
Central Processor Unit (CPU)
3.1 Introduction
This section presents information on M68HC11 central processor unit (CPU):
• Architecture
• Data types
• Addressing modes
• Instruction set
• Special operations such as subroutine calls and interrupts
The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as
addresses in the 64-Kbyte memory map. This is referred to as memory-mapped I/O. I/O has no
instructions separate from those used by memory. This architecture also allows accessing an operand
from an external memory location with no execution time penalty.
3.2 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory
locations. The seven registers, discussed in the following paragraphs, are shown in Figure 3-1.
Figure 3-1. Programming Model
A:B
7070
15 0
ACCUMULATOR A ACCUMULATOR B
DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
70
CVZNIHXS
D
IX
IY
SP
PC
CARRY
OVERFLOW
ZERO
NEGATIVE
I INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X INTERRUPT MASK
STOP DISABLE
CCR
15
15
15
15
0
0
0
0
CONDITION CODE REGISTER