Datasheet

Electrical Characteristics
MC68HC711D3 Data Sheet, Rev. 2.1
118 Freescale Semiconductor
Figure 9-11. SPI Master Timing (CPHA = 0)
Figure 9-12. SPI Master Timing (CPHA = 1)
SEE
NOTE
Note: This first clock edge is generated internally but is not seen at the SCK pin.
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
(INPUT)
1
SEE
NOTE
11
MSB IN
BIT 6 - - - -1
LSB IN
MASTER MSB OUT MASTER LSB OUT
BIT 6 - - - -1
10
12
13
SS
IS HELD HIGH ON MASTER
5
4
13
12
11 (REF)10 (REF)
13
4
5
12
Note: This last clock edge is generated internally but is not seen at the SCK pin.
4
5
5
4
1
SEE
NOTE
11
6
7
MSB IN LSB IN
MASTER MSB OUT MASTER LSB OUTBIT 6 - - - -1
10
13
12
12
13
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
(INPUT)
SS IS HELD HIGH ON MASTER
SEE
NOTE
12
13
BIT 6 - - - -1
11 (REF)10 (REF)