Datasheet

Serial Peripheral Interface Timing
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor 117
9.9 Serial Peripheral Interface Timing
Num
Characteristic
(1)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
. All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless
otherwise noted.
Symbol
2.0 MHz 3.0 MHz
Unit
Min Max Min Max
Operating frequency
Master
Slave
f
op(m)
f
op(s)
dc
dc
0.5
2.0
dc
dc
0.5
3.0
f
op
MHz
1
Cycle time
Master
Slave
t
cyc(m)
t
CYC(s)
2.0
500
—
—
2.0
333
—
—
t
cyc
ns
2
Enable lead time
Master
(2)
Slave
2. Signal production depends on software.
t
lead(m)
t
lead(s)
—
250
—
—
—
240
—
—
ns
3
Enable lag time
Master
(2)
Slave
t
lag(m)
t
lag(s)
—
250
—
—
—
240
—
—
ns
4
Clock (SCK) high time
Master
Slave
t
w(SCKH)m
t
w(SCKH)s
340
190
—
—
227
127
—
—
ns
5
Clock (SCK) low time
Master
Slave
t
w(SCKL)m
t
w(SCKL)s
340
190
—
—
227
127
—
—
ns
6
Data setup time (inputs)
Master
Slave
t
su(m)
t
su(s)
100
100
—
—
100
100
—
—
ns
7
Data hold time (inputs)
Master
Slave
t
h(m)
t
h(s)
100
100
—
—
100
100
—
—
ns
8
Access time (time to data active from high-impedance state)
Slave
t
a
0 120 0 120 ns
9
Disable time (hold time to high-impedance state)
Slave
t
dis
— 240 — 167 ns
10
Data valid (after enable edge)
(3)
3. Assumes 200 pF load on all SPI pins.
t
v(s)
— 240 — 167 ns
11 Data hold time (outputs) (after enable edge)
t
ho
0—0—ns
12
Rise time (20% V
DD
to 70% V
DD
, C
L
= 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS
)
t
rm
t
rs
—
—
100
2.0
—
—
100
2.0
ns
µs
13
Fall time (70% V
DD
to 20% V
DD
, C
L
= 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS
)
t
fm
t
fs
—
—
100
2.0
—
—
100
2.0
ns
µs