Datasheet

Electrical Characteristics
MC68HC711D3 Data Sheet, Rev. 2.1
114 Freescale Semiconductor
9.7 Peripheral Port Timing
Figure 9-8. Port Write Timing Diagram
Figure 9-9. Port Read Timing Diagram
Characteristic
(1)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
. All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless
otherwise noted.
Symbol
1.0 MHz 2.0 MHz 3.0 MHz
Unit
Min Max Min Max Min Max
Frequency of operation (E-clock frequency)
f
O
1.0 1.0 2.0 2.0 3.0 3.0 MHz
E-clock period
t
CYC
1000 — 500 — 333 — ns
Peripheral data setup time
(2)
MCU read of ports A, B, C, and D
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).
t
PDSU
100 — 100 — 100 — ns
Peripheral data hold time
(2)
MCU read of ports A, B, C, and D
t
PDH
50 — 50 — 50 — ns
Delay time, peripheral data write
MCU write to port A
MCU writes to ports B, C, and D
t
PWD
= 1/4 t
cyc
+ 150 ns
t
PWD
—
—
200
350
—
—
200
225
—
—
200
183
ns
t
PWD
E
MCU WRITE TO PORT
PREVIOUS PORT DATA
PREVIOUS PORT DATA
NEW DATA VALID
NEW DATA VALID
PORTS
B, C, D
PORT A
t
PWD
t
PDH
E
MCU READ OF PORT
t
PDSU
PORTS
A, B, C, D