Datasheet

Control Timing
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor 109
9.6 Control Timing
Figure 9-3. Timer Inputs
Characteristic
(1)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
. All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless
otherwise noted.
Symbol
1.0 MHz 2.0 MHz 3.0 MHz
Unit
Min Max Min Max Min Max
Frequency of operation
f
O
dc 1.0 dc 2.0 dc 3.0 MHz
E-clock period
t
cyc
1000 — 500 — 333 — ns
Crystal frequency
f
XTAL
—4.0—8.0—12.0MHz
External oscillator frequency
4 f
O
dc 4.0 dc 8.0 dc 12.0 MHz
Processor control setup timet
PCSU
= 1/4 t
cyc
+ 50 ns t
PCSU
300 — 175 — 133 — ns
Reset input pulse width
(2)
To guarantee external reset vector
Minimum input time can be preempted by internal reset
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 5
Input/Output (I/O) Ports for further details.
PW
RSTL
8
1
—
—
8
1
—
—
8
1
—
—
t
cyc
Mode programming setup time
t
MPS
2—2—2—
t
cyc
Mode programming hold time
t
MPH
10 — 10 — 10 — ns
Interrupt pulse width, PW
IRQ
= t
cyc
+ 20 ns
IRQ
edge-sensitive mode
PW
IRQ
1020 — 520 — 353 — ns
Wait recovery startup time
t
WRS
— 4—4—4
t
cyc
Timer pulse width PW
TIM
= t
cyc
+ 20 ns
Input capture pulse
Accumulator input
PW
TIM
1020 — 520 — 353 — ns
Notes:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA7
(2) (3)
PA7
(1) (3)
PA0–PA3
(2)
PA0–PA3
(1)
PW
TIM