Datasheet

MC68331TS/D 9
2 Signal Descriptions
2.1 Pin Characteristics
The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All
inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin
function. Refer to Table 4 , for a description of output drivers. An entry in the discrete I/O column of Ta-
ble 2 indicates that a pin has an alternate I/O function. The port designation is given when it applies.
Refer to the MCU Block Diagram for information about port organization.
Table 2 MCU Pin Characteristics
Pin
Mnemonic
Output
Driver
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Port
Designation
ADDR23/CS10
/ECLK A Y N O —
ADDR[22:19]/CS[9:6]
A Y N O PC[6:3]
ADDR[18:0] A Y N — —
AS
B Y N I/O PE5
AVEC
B Y N I/O PE2
BERR
BY N — —
BG
/CS1 B — — — —
BGACK
/CS2 B Y N — —
BKPT
/DSCLK — Y Y — —
BR
/CS0 BY N ——
CLKOUT A — — — —
CSBOOT
B — — — —
DATA[15:0]
1
Aw Y N — —
DS
B Y N I/O PE4
DSACK1
B Y N I/O PE1
DSACK0
B Y N I/O PE0
DSI/IFETCH
AY Y ——
DSO/IPIPE
A— — ——
EXTAL
2
— — Special — —
FC[2:0]/CS[5:3] A Y N O PC[2:0]
FREEZE/QUOT A — — — —
IC4/OC5 A Y Y I/O GP4
IC[3:1] A Y Y I/O GP[7:5]
HALT
Bo Y N — —
IRQ[7:1]
B Y Y I/O PF[7:1]
MISO Bo Y Y I/O PQS0
MODCLK
1
B Y N I/O PF0
MOSI Bo Y Y I/O PQS1
OC[4:1] A Y Y I/O GP[3:0]
PAI
3
— Y Y I —
PCLK
3
— Y Y I —
PCS0
/SS Bo Y Y I/O PQS3
PCS[3:1]
Bo Y Y I/O PQS[6:4]
PWMA, PWMB A — — O —
R/W
AY N — —
RESET
Bo Y Y — —
RMC
B Y N I/O PE3
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