Datasheet

74 MC68331TS/D

Figure 18 PWM Unit Block Diagram

6.3 Pulse-Width Modulator

The pulse-width modulation submodule has two output pins. The outputs are periodic waveforms con-

trolled by a single frequency whose duty cycles can be independently selected and modified by user

software. Each PWM can be independently programmed to run in fast or slow mode. The PWM unit has

its own 16-bit free-running counter, which is clocked by an output of the nine-stage prescaler (the same

prescaler used by the capture/compare unit) or by the clock input pin, PCLK.

16/32 PWM BLOCK BLOCK

ZERO DETECTOR

16-BIT COUNTER

PWMA REGISTER PWMB REGISTER

PWMABUF REGISTER PWMBBUF REGISTER

"A" COMPARATOR "B" COMPARATOR

"A" MULTIPLEXER "B" MULTIPLEXER

SFB

BIT

SFA

BIT

F1A

BIT

F1B

BIT

LATCH

ZERO DETECTOR

PWMB

PWMA

FROM

PRESCALER CLOCK

[14:0]

16-BIT DATA BUS

8-BIT

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Freescale Semiconductor, Inc.

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