Datasheet

MC68331TS/D 71

Y = M111, where M is the logic state of the modmap (MM) bit in SIMCR.

6.2 Capture/Compare Unit

The capture/compare unit features three input capture channels, four output compare channels, and

one input capture/output compare channel (function selected by control register). These channels share

a 16-bit free-running counter (TCNT), which derives its clock from seven stages of a 9-stage prescaler

or from external clock input PCLK. This section, which is similar to the timer found on the MC68HC11F1,

also contains one pulse accumulator channel. The pulse accumulator logic includes its own 8-bit

counter and can operate in either event counting mode or gated time accumulation mode. Refer to the

following block diagrams of the GPT timer and prescaler.

Table 26 GPT Address Map

Access Address 15 8 7 0

S $YFF900 GPT MODULE CONFIGURATION (GPTMCR)

S $YFF902 (RESERVED FOR TEST)

S $YFF904 INTERRUPT CONFIGURATION (ICR)

U $YFF906 PGP DATA DIRECTION (DDRGP) PGP DATA (PORTGP)

U $YFF908 OC1 ACTION MASK (OC1M) OC1 ACTION DATA (OC1D)

U $YFF90A TIMER COUNTER (TCNT)

U $YFF90C PA CONTROL (PACTL) PA COUNTER (PACNT)

U $YFF90E INPUT CAPTURE 1 (TIC1)

U $YFF910 INPUT CAPTURE 2 (TIC2)

U $YFF912 INPUT CAPTURE 3 (TIC3)

U $YFF914 OUTPUT COMPARE 1 (TOC1)

U $YFF916 OUTPUT COMPARE 2 (TOC2)

U $YFF918 OUTPUT COMPARE 3 (TOC3)

U $YFF91A OUTPUT COMPARE 4 (TOC4)

U $YFF91C INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)

U $YFF91E TIMER CONTROL 1 (TCTL1) TIMER CONTROL 2 (TCTL2)

U $YFF920 TIMER MASK 1 (TMSK1) TIMER MASK 2 (TMSK2)

U $YFF922 TIMER FLAG 1 (TFLG1) TIMER FLAG 2 (TFLG2)

U $YFF924 FORCE COMPARE (CFORC) PWM CONTROL C (PWMC)

U $YFF926 PWM CONTROL A (PWMA) PWM CONTROL B (PWMB)

U $YFF928 PWM COUNT (PWMCNT)

U $YFF92A PWMA BUFFER (PWMBUFA) PWMB BUFFER (PWMBUFB)

U $YFF92C GPT PRESCALER (PRESCL)

$YFF92E–

$YFF93F

NOT USED

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Freescale Semiconductor, Inc.

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