Datasheet

MC68331TS/D 55
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins.
To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS.
Clearing a bit in the PQSPAR assigns the corresponding pin to general-purpose I/O; setting a bit as-
signs the pin to the QSPI. The PQSPAR does not affect operation of the SCI.
NOTES:
1. PQS2 is a digital I/O pin unless the SPI is enabled
(SPE in SPCR1 set), in which case it becomes SPI
serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter
is enabled (TE in SCCR1 = 1), in which case it be-
comes SCI serial output TXD.
PORTQS — Port QS Data Register $YFFC14
15 8 7 6 5 4 3 2 1 0
NOT USED PQS7 PQS6 PQS5 PQS4 PQS3 PQS2 PQS1 PQS0
RESET:
0 0 0 0 0 0 0 0
PQSPAR — PORT QS Pin Assignment Register $YFFC16
DDRQS — PORT QS Data Direction Register $YFFC17
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
PQSPA6 PQSPA5 PQSPA4 PQSPA3
0
PQSPA1 PQSPA0
DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 23 QSPAR Pin Assignments
PQSPAR Field PQSPAR Bit Pin Function
PQSPA0 0
1
PQS0
MISO
PQSPA1 0
1
PQS1
MOSI
PQSPA2 0
1
PQS2
1
SCK
PQSPA3 0
1
PQS3
PCS0/SS
PQSPA4 0
1
PQS4
PCS1
PQSPA5 0
1
PQS5
PCS2
PQSPA6 0
1
PQS6
PCS3
PQSPA7 0
1
PQS7
2
TXD
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