Datasheet

MC68331TS/D 49
1. Privileged instruction.
SUB <ea>, Dn
Dn, <ea>
8, 16, 32
Destination − Source ⇒ Destination
SUBA <ea>, An 16, 32
Destination − Source ⇒ Destination
SUBI #<data>, <ea> 8, 16, 32
Destination − Data ⇒ Destination
SUBQ #<data>, <ea> 8, 16, 32
Destination − Data ⇒ Destination
SUBX Dn, Dn
− (An), − (An)
8, 16, 32
8, 16, 32
Destination − Source − X ⇒ Destination
SWAP Dn 16
TAS <ea> 8
Destination Tested Condition Codes bit 7 of
Destination
TBLS/TBLU <ea>, Dn
Dym : Dyn, Dn
8, 16, 32
Dyn − Dym ⇒ Temp
(Temp ∗ Dn [7 : 0]) ⇒ Temp
(Dym ∗ 256) + Temp ⇒ Dn
TBLSN/TBLUN <ea>, Dn
Dym : Dyn, Dn
8, 16, 32
Dyn − Dym ⇒ Temp
(Temp ∗ Dn [7 : 0]) / 256 ⇒ Temp
Dym + Temp ⇒ Dn
TRAP #<data> none
SSP − 2 ⇒ SSP; format/vector offset ⇒ (SSP);
SSP − 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP);
vector address ⇒ PC
TRAPcc none
#<data>
none
16, 32
If cc true, then TRAP exception
TRAPV none none
If V set, then overflow TRAP exception
TST <ea> 8, 16, 32
Source − 0, to set condition codes
UNLK An 32
An ⇒ SP; (SP) ⇒ An, SP + 4 ⇒ SP
Table 20 Instruction Set Summary (Continued)
Instruction Syntax Operand Size Operation
MSW LSW
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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