Datasheet

48 MC68331TS/D
MOVEP Dn, (d16, An)
(d16, An), Dn
16, 32
Dn [31 : 24] ⇒ (An + d); Dn [23 : 16] ⇒ (An + d + 2);
Dn [15 : 8] ⇒ (An + d + 4); Dn [7 : 0] ⇒ (An + d + 6)
(An + d) ⇒ Dn [31 : 24]; (An + d + 2) ⇒ Dn [23 : 16];
(An + d + 4) ⇒ Dn [15 : 8]; (An + d + 6) ⇒ Dn [7 : 0]
MOVEQ #<data>, Dn 8 ⇒ 32
Immediate data ⇒ Destination
MOVES
1
Rn, <ea>
<ea>, Rn
8, 16, 32
Rn ⇒ Destination using DFC
Source using SFC ⇒ Rn
MULS/MULU <ea>, Dn
<ea>, Dl
<ea>, Dh : Dl
16 ∗ 16 ⇒ 32
32 ∗ 32 ⇒ 32
32 ∗ 32 ⇒ 64
Source ∗ Destination ⇒ Destination
(signed or unsigned)
NBCD <ea> 8
8
0 − Destination
10
− X ⇒ Destination
NEG <ea> 8, 16, 32
0 − Destination ⇒ Destination
NEGX <ea> 8, 16, 32
0 − Destination − X ⇒ Destination
NOP none none
PC + 2 ⇒ PC
NOT <ea> 8, 16, 32
Destination
⇒ Destination
OR <ea>, Dn
Dn, <ea>
8, 16, 32
8, 16, 32
Source + Destination ⇒ Destination
ORI #<data>, <ea> 8, 16, 32
Data + Destination ⇒ Destination
ORI to CCR #<data>, CCR 16
Source + CCR ⇒ SR
ORI to SR
1
#<data>, SR 16
Source ; SR ⇒ SR
PEA <ea> 32
SP − 4 ⇒ SP; <ea> ⇒ SP
RESET
1
none none
Assert RESET
line
ROL Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ROR Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ROXL Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ROXR Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
RTD #d 16
(SP) ⇒ PC; SP + 4 + d ⇒ SP
RTE
1
none none
(SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC;
SP + 4 ⇒ SP;
Restore stack according to format
RTR none none
(SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC;
SP + 4 ⇒ SP
RTS none none
(SP) ⇒ PC; SP + 4 ⇒ SP
SBCD Dn, Dn
− (An), − (An)
8
8
Destination10 − Source10 − X ⇒ Destination
Scc <ea> 8
If condition true, then destination bits are set to 1;
else, destination bits are cleared to 0
STOP
1
#<data> 16
Data ⇒ SR; STOP
Table 20 Instruction Set Summary (Continued)
Instruction Syntax Operand Size Operation
C
C
C X
CX
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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