Datasheet

MC68331TS/D 47
CMPM (An) +, (An) + 8, 16, 32
(Destination − Source), CCR shows results
CMP2 <ea>, Rn 8, 16, 32
Lower bound ≤ Rn ≤ Upper bound, CCR shows result
DBcc Dn, label 16
If condition false, then Dn − 1 ⇒ PC;
if Dn ≠ (− 1), then PC + d ⇒ PC
DIVS/DIVU <ea>, Dn 32/16 ⇒ 16 : 16
Destination / Source ⇒ Destination
(signed or unsigned)
DIVSL/DIVUL <ea>, Dr : Dq
<ea>, Dq
<ea>, Dr : Dq
64/32 ⇒ 32 : 32
32/32 ⇒ 32
32/32 ⇒ 32 : 32
Destination / Source ⇒ Destination
(signed or unsigned)
EOR Dn, <ea> 8, 16, 32
Source ⊕ Destination ⇒ Destination
EORI # <data>, <ea> 8, 16, 32
Data ⊕ Destination ⇒ Destination
EORI to CCR # <data>, CCR 8
Source ⊕ CCR ⇒ CCR
EORI to SR
1
# <data>, SR 16
Source ⊕ SR ⇒ SR
EXG Rn, Rn 32
Rn ⇒ Rn
EXT Dn
Dn
8 ⇒ 16
16 ⇒ 32
Sign extended Destination ⇒ Destination
EXTB Dn 8 ⇒ 32
Sign extended Destination ⇒ Destination
ILLEGAL none none
SSP − 2 ⇒ SSP; vector offset ⇒ (SSP);
SSP − 4 ⇒ SSP; PC ⇒ (SSP);
SSP − 2 ⇒ SSP; SR ⇒ (SSP);
Illegal instruction vector address ⇒ PC
JMP <ea> none
Destination ⇒ PC
JSR <ea> none
SP − 4 ⇒ SP; PC ⇒ (SP); destination ⇒ PC
LEA <ea>, An 32
<ea> ⇒ An
LINK An, # d 16, 32
SP − 4 ⇒ SP, An ⇒ (SP); SP ⇒ An, SP + d ⇒ SP
LPSTOP
1
# <data> 16
Data ⇒ SR; interrupt mask ⇒ EBI; STOP
LSL Dn, Dn
# <data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
LSR Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
MOVE <ea>, <ea> 8, 16, 32
Source ⇒ Destination
MOVEA <ea>, An 16, 32 ⇒ 32
Source ⇒ Destination
MOVEA
1
USP, An
An, USP
32
32
USP ⇒ An
An ⇒ USP
MOVE from CCR CCR, <ea> 16
CCR ⇒ Destination
MOVE to CCR <ea>, CCR 16
Source ⇒ CCR
MOVE from SR
1
SR, <ea> 16
SR ⇒ Destination
MOVE to SR
1
<ea>, SR 16
Source ⇒ SR
MOVE USP
1
USP, An
An, USP
32
32
USP ⇒ An
An ⇒ USP
MOVEC
1
Rc, Rn
Rn, Rc
32
32
Rc ⇒ Rn
Rn ⇒ Rc
MOVEM list, <ea>
<ea>, list
16, 32
16, 32 ⇒ 32
Listed registers ⇒ Destination
Source ⇒ Listed registers
Table 20 Instruction Set Summary (Continued)
Instruction Syntax Operand Size Operation
X/C 0
X/C
0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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