Datasheet
12 MC68331TS/D
Boot Chip Select CSBOOT
Chip select for external boot startup ROM
Data Bus DATA[15:0] 16-bit data bus
Data Strobe DS
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle, indi-
cates that valid data is on the data bus.
Data and Size Acknowledge DSACK[1:0]
Provide asynchronous data transfers and dynamic bus sizing
Development Serial In, Out,
Clock
DSI, DSO,
DSCLK
Serial I/O and clock for background debugging mode
Crystal Oscillator EXTAL, XTAL Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Function Codes FC[2:0] Identify processor state and current address space
Freeze FREEZE Indicates that the CPU has entered background mode
Halt HALT
Suspend external bus activity
Input Capture IC[3:1] When a specified transition is detected on an input capture pin, the
value in an internal GPT counter is latched
Input Capture 4/Output Compare
5
IC4/OC5 Can be configured for either an input capture or output compare
Instruction Pipeline IPIPE
, IFETCH Indicate instruction pipeline activity
Interrupt Request Level IRQ[7:1]
Provides an interrupt priority level to the CPU
Master In Slave Out MISO Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Clock Mode Select MODCLK Selects the source and type of system clock
Master Out Slave In MOSI Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Output Compare OC[5:1] Change state when the value of an internal GPT counter matches
a value stored in a GPT control register
Pulse Accumulator Input PAI Signal input to the pulse accumulator
Port C PC[6:0] SIM digital output port signals
Auxiliary Timer Clock Input PCLK External clock dedicated to the GPT
Peripheral Chip Select PCS[3:0] QSPI peripheral chip selects
Port E PE[7:0] SIM digital I/O port signals
Port F PF[7:0] SIM digital I/O port signals
Port QS PQS[7:0] QSM digital I/O port signals
Pulse-Width Modulation PWMA, PWMB Output for PWM
Quotient Out QUOT Provides the quotient bit of the polynomial divider
Reset RESET
System reset
Read-Modify-Write Cycle RMC
Indicates an indivisible read-modify-write instruction
Read/Write R/W
Indicates the direction of data transfer on the bus
SCI Receive Data RXD Serial input to the SCI
QSPI Serial Clock SCK Clock output from QSPI in master mode;
clock input to QSPI in slave mode
Size SIZ[1:0] Indicates the number of bytes to be transferred during a bus cycle
Slave Select SS
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
Three-State Control TSC Places all output drivers in a high-impedance state
SCI Transmit Data TXD Serial output from the SCI
External Filter Capacitor XFC Connection for external phase-locked loop filter capacitor
Table 6 MCU Signal Function (Continued)
Signal Name Mnemonic Function
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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