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by MC68331TS/D Rev. 2

MC68331

Technical Summary

32-Bit Modular Microcontroller

1 Introduction

The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipula-

tion capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that

interface through a common intermodule bus (IMB). Standardization facilitates rapid development of

devices tailored for specific applications.

The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a general-purpose

timer (GPT), and a queued serial module (QSM).

The MCU can either synthesize an internal clock signal from an external reference or use an external

clock input directly. Operation with a 32.768-kHz reference frequency is standard. The maximum sys-

tem clock speed is 20.97 MHz. Because MCU operation is fully static, register and memory contents

are not affected by a loss of clock.

High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power

consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The

CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this

capability.

Freescale Semiconductor, I

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Freescale Semiconductor

Summary of content (84 pages)

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Freescale Semiconductor Order this document by MC68331TS/D Rev. 2 MC68331 Technical Summary 32-Bit Modular Microcontroller 1 Introduction Freescale Semiconductor, Inc... The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB).
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Freescale Semiconductor, Inc. Table 1 Ordering Information Package Type Temperature 132-Pin PQFP –40 to +85 °C Frequency (MHz) 16 MHz 20 MHz –40 to +105 °C 16 MHz 20 MHz –40 to +125 °C 16 MHz Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. TABLE OF CONTENTS Section 1 1.1 1.2 1.3 1.4 1.5 2 Freescale Semiconductor, Inc... 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.2 6.3 6.4 7 Page Introduction 1 Features ......................................................................................................................................4 Block Diagram ........................................................................................
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1.
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Freescale Semiconductor, Inc. 1.
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Freescale Semiconductor, Inc.
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144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MC68331 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC VSS PE4/AS PE6/SIZ0 PE7/SIZ1 R/W PF0/MODCLK PF1/IRQ1 PF2/IRQ2 PF3/IRQ3 PF4/IRQ4 PF5/IRQ5 PF6/IRQ6 PF7/IRQ7 BERR HALT RESET VSS CLKOUT VDD
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Freescale Semiconductor, Inc. 1.4 Address Map The following figure is a map of the MCU internal addresses. Unimplemented blocks are mapped externally. $YFF000 $YFF900 GPT Freescale Semiconductor, Inc... $YFF93F $YFFA00 SIM $YFFA7F $YFFA80 $YFFAFF RESERVED $YFFC00 QSM $YFFDFF $YFFFFF 331 ADDRESS MAP Figure 4 MCU Address Map 1.5 Intermodule Bus The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of modular microcontrollers.
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Freescale Semiconductor, Inc. 2 Signal Descriptions 2.1 Pin Characteristics The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. Refer to Table 4, for a description of output drivers. An entry in the discrete I/O column of Table 2 indicates that a pin has an alternate I/O function. The port designation is given when it applies.
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Freescale Semiconductor, Inc. Table 2 MCU Pin Characteristics (Continued) Freescale Semiconductor, Inc... Pin Mnemonic RXD SCK SIZ[1:0] TSC TXD XFC2 Output Driver — Bo B — Bo — Input Synchronized N Y Y Y Y — Input Hysteresis N Y N Y Y — Discrete I/O — I/O I/O — I/O Special Port Designation — PQS2 PE[7:6] — PQS7 — XTAL2 — — — Special — NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin. 2.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Table 6 MCU Signal Function (Continued) Signal Name Boot Chip Select Data Bus Data Strobe Data and Size Acknowledge Development Serial In, Out, Clock Freescale Semiconductor, Inc... Crystal Oscillator Function Codes Freeze Halt Input Capture Mnemonic CSBOOT DATA[15:0] DS Function Chip select for external boot startup ROM 16-bit data bus During a read cycle, indicates when it is possible for an external device to place data on the data bus.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68331TS/D For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 3 System Integration Module The system integration module (SIM) consists of five functional blocks that control system start-up, initialization, configuration, and external bus. SYSTEM CONFIGURATION CLOCK SYNTHESIZER XTAL CLKOUT EXTAL MODCLK Freescale Semiconductor, Inc... SYSTEM PROTECTION CHIP SELECTS CHIP SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE RESET FACTORY TEST TSC FREEZE/QUOT 300 S(C)IM BLOCK Figure 5 SIM Block Diagram 3.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... RESET STATUS HALT MONITOR RESET REQUEST BUS MONITOR BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG TIMER CLOCK RESET REQUEST PRESCALER 29 PERIODIC INTERRUPT TIMER IRQ[7:1] 300 SYS PROTECT BLOCK Figure 6 System Configuration and Protection Block 3.2.1 System Configuration The SIM controls MCU configuration during normal operation and during internal testing.
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Freescale Semiconductor, Inc. SLVEN —Factory Test Mode Enabled This bit is a read-only status bit that reflects the state of DATA11 during reset. 0 = IMB is not available to an external master. 1 = An external bus master has direct access to the IMB. Freescale Semiconductor, Inc... SHEN[1:0] —Show Cycle Enable This field determines what the EBI does with the external bus during internal transfer operations. A show cycle allows internal transfers to be externally monitored.
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Freescale Semiconductor, Inc. SWP —Software Watchdog Prescale This bit controls the value of the software watchdog prescaler. 0 = Software watchdog clock not prescaled 1 = Software watchdog clock prescaled by 512 Freescale Semiconductor, Inc... SWT[1:0] —Software Watchdog Timing This field selects the divide ratio used to establish software watchdog time-out period. The following table gives the ratio for each combination of SWP and SWT bits.
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Freescale Semiconductor, Inc. 3.2.5 Spurious Interrupt Monitor The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-acknowledge cycle. 3.2.6 Software Watchdog The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog times out and issues a reset. This register can be written at any time, but returns zeros when read.
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Freescale Semiconductor, Inc. PIRQL 000 001 010 011 100 101 110 111 Interrupt Request Level Periodic Interrupt Disabled Interrupt Request Level 1 Interrupt Request Level 2 Interrupt Request Level 3 Interrupt Request Level 4 Interrupt Request Level 5 Interrupt Request Level 6 Interrupt Request Level 7 Freescale Semiconductor, Inc... PIV[7:0] —Periodic Interrupt Vector The bits of this field contain the vector generated in response to an interrupt from the periodic timer.
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Freescale Semiconductor, Inc. 32.768 KHz 22 pF 2 R4 330K R3 10M VSSI V DDSYN 2 1 XFC XTAL CRYSTAL OSCILLATOR 0.1µF 0.01µF 0.1µF VSSI EXTAL Freescale Semiconductor, Inc... 22 pF XFC PIN PHASE COMPARATOR VSSI VDDSYN LOW-PASS FILTER FEEDBACK DIVIDER SYSTEM CLOCK CONTROL VCO W Y X SYSTEM CLOCK 1. MUST BE LOW-LEAKAGE CAPACITOR (INSULATION RESISTANCE 30,000 MΩ OR GREATER). 2. RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL.
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Freescale Semiconductor, Inc. 3.3.2 Clock Synthesizer Operation A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator. The other phase comparator input is a reference signal, either from the internal oscillator or from an external source. The comparator generates a control signal proportional to the difference in phase between its two inputs.
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Freescale Semiconductor, Inc. When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks. The SYNCR can be read or written only when the CPU is operating at the supervisor privilege level. W —Frequency Control (VCO) This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO speed by a factor of four.
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Freescale Semiconductor, Inc. Port width is the maximum number of bits accepted or provided during a bus transfer. External devices must follow the handshake protocol described below. Control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. The selected device controls the length of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data.
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Freescale Semiconductor, Inc. 3.4.4 Address Strobe AS is a timing signal that indicates the validity of an address on the address bus and the validity of many control signals. It is asserted one-half clock after the beginning of a bus cycle. 3.4.5 Data Bus Data bus signals DATA[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle.
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Freescale Semiconductor, Inc. For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACK0 and DSACK1 signals to indicate the port width.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. INTERNAL SIGNALS BASE ADDRESS REGISTER ADDRESS ADDRESS COMPARATOR BUS CONTROL TIMING AND CONTROL PIN OPTION COMPARE Freescale Semiconductor, Inc... OPTION REGISTER AVEC AVEC GENERATOR DSACK GENERATOR PIN ASSIGNMENT REGISTER PIN DATA REGISTER DSACK CHIP SEL BLOCK Figure 9 Chip-Select Circuit Block Diagram The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU.
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Freescale Semiconductor, Inc. 3.5.2 Pin Assignment Registers The pin assignment registers (CSPAR0 and CSPAR1) contain pairs of bits that determine the function of chip-select pins. The pin assignment encodings used in these registers are shown below. Table 12 Pin Assignment Encodings Bit Field 00 01 10 11 Description Discrete Output Alternate Function Chip Select (8-Bit Port) Chip Select (16-Bit Port) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. At reset, either the alternate function (01) or chip-select function (11) can be encoded. DATA pins are driven to logic level one by a weak internal pull-up during reset. Encoding is for chip-select function unless a data line is held low during reset. Note that bus loading can overcome the weak pull-up and hold pins low during reset. The following table shows the hierarchical selection method that determines the reset functions of pins controlled by CSPAR1.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Block Size Field 000 001 010 011 100 101 110 111 Block Size 2K 8K 16 K 64 K 128 K 256 K 512 K 1M Address Lines Compared ADDR[23:11] ADDR[23:13] ADDR[23:14] ADDR[23:16] ADDR[23:17] ADDR[23:18] ADDR[23:19] ADDR[23:20] ADDR[23:11] —Base Address Field This field sets the starting address of a particular address space. The address compare logic uses only the most significant bits to match an address within a block.
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Freescale Semiconductor, Inc. Byte 00 01 10 11 Description Disable Lower Byte Upper Byte Both Bytes Freescale Semiconductor, Inc... R/W —Read/Write This field causes a chip select to be asserted only for a read, only for a write, or for both read and write. Refer to the following table for options available.
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Freescale Semiconductor, Inc. SPACE —Address Space Use this option field to select an address space for the chip-select logic. The CPU32 normally operates in supervisor or user space, but interrupt acknowledge cycles must take place in CPU space. Space Field 00 01 10 11 Address Space CPU Space User Space Supervisor Space Supervisor/User Space Freescale Semiconductor, Inc... IPL —Interrupt Priority Level If the space field is set for CPU space (00), chip-select logic can be used for interrupt acknowledge.
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Freescale Semiconductor, Inc. 3.6 General-Purpose Input/Output SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs describe registers that control the ports. PORTE0, PORTE1 —Port E Data Register 15 $YFFA11, $YFFA13 8 NOT USED 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 U U U U U U U U RESET: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. PORTF0, PORTF1 — Port F Data Register 15 $YFFA19, $YFFA1B 8 NOT USED 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 U U U U U U U U RESET: The write to the port F data register is stored in the internal data latch, and if any port F pin is configured as an output, the value stored for that bit is driven onto the pin. A read of the port F data register returns the value at the pin only if the pin is configured as a discrete input.
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Freescale Semiconductor, Inc. 3.7 Resets Reset procedures handle system initialization and recovery from catastrophic failure. The MCU performs resets with a combination of hardware and software. The system integration module determines whether a reset is valid, asserts control signals, performs basic system configuration based on hardware mode-select inputs, then passes control to the CPU. Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.
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Freescale Semiconductor, Inc. Table 19 Module Pin Functions Module CPU32 GPT Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15 milliseconds. During this period, module port pins may be in an indeterminate state.
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Freescale Semiconductor, Inc. Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete.
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Freescale Semiconductor, Inc. 3.8.2 Interrupt Processing Summary Freescale Semiconductor, Inc... A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt service request has been detected and is pending. A. The CPU finishes higher priority exception processing or reaches an instruction boundary. B. Processor state is stacked. The contents of the status register and program counter are saved. C. The interrupt acknowledge cycle begins: 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 42 For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. 4 Central Processor Unit Based on the powerful MC68020, the CPU32 processing module provides enhanced system performance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview Freescale Semiconductor, Inc... The CPU32 is fully object code compatible with the M68000 Family, which excels at processing calculation-intensive algorithms and supporting high-level languages.
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Freescale Semiconductor, Inc. 31 16 15 8 7 0 D0 D1 D2 D3 Data Registers D4 D5 D6 D7 31 16 15 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. 4.3 Status Register The status register contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The lower byte containing the condition codes is the only portion of the register available at the user privilege level; it is referenced as the condition code register (CCR) in user programs.
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Freescale Semiconductor, Inc. 4.6 Instruction Set Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Table 20 Instruction Set Summary (Continued) Instruction Syntax Operand Size MOVEP Dn, (d16, An) 16, 32 (An + d) ⇒ Dn [31 : 24]; (An + d + 2) ⇒ Dn [23 : 16]; (An + d + 4) ⇒ Dn [15 : 8]; (An + d + 6) ⇒ Dn [7 : 0] (d16, An), Dn Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. 4.7 Background Debugging Mode The background debugger on the CPU32 is implemented in CPU microcode. The background debugging commands are summarized below. Table 21 Background Debugging Mode Command Read D/A Register Write D/A Register Read System Register Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. 5 Queued Serial Module The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6 INTERFACE LOGIC PORT QS IMB Freescale Semiconductor, Inc... QSPI TXD/PQS7 SCI RXD QSM BLOCK Figure 12 QSM Block Diagram 5.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. 5.3 QSM Registers QSM registers are divided into four categories: QSM global registers, QSM pin control registers, QSPI submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate sections below. Writes to unimplemented register bits have no meaning or effect, and reads from unimplemented bits always return a logic zero value.
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Freescale Semiconductor, Inc. QTEST — QSM Test Register $YFFC02 QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU is in test mode. QILR — QSM Interrupt Levels Register 15 14 0 0 13 11 $YFFC04 10 ILQSPI 8 7 0 ILSCI QIVR RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... QILR determines the priority level of interrupts requested by the QSM and the vector used when an interrupt is acknowledged.
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Freescale Semiconductor, Inc. PORTQS — Port QS Data Register $YFFC14 15 8 7 NOT USED PQS7 6 5 4 3 2 1 0 PQS6 PQS5 PQS4 PQS3 PQS2 PQS1 PQS0 0 0 0 0 0 0 RESET: 0 0 PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins. To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS. PQSPAR — PORT QS Pin Assignment Register DDRQS — PORT QS Data Direction Register 15 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function. Table 24 Effect of DDRQS on QSM Pin Function QSM Pin Mode MISO Master DDRQS Bit DDQ0 Slave MOSI Master DDQ1 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. QUEUE CONTROL BLOCK QUEUE POINTER COMPARATOR 4 A D D R E S S DONE 4 Freescale Semiconductor, Inc... END QUEUE POINTER 80-BYTE QSPI RAM R E G I S T E R CONTROL LOGIC STATUS REGISTER CONTROL REGISTERS 4 DELAY COUNTER CHIP SELECT 4 COMMAND MSB LSB 8/16-BIT SHIFT REGISTER PROGRAMMABLE LOGIC ARRAY M S MOSI Rx/Tx DATA REGISTER M S MISO PCS0/SS 2 PCS[2:1] BAUD RATE GENERATOR SCK QSPI BLOCK Figure 13 QSPI Block Diagram 5.4.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. MSTR — Master/Slave Mode Select 0 = QSPI is a slave device and only responds to externally generated serial data. 1 = QSPI is system master and can initiate transmission to external SPI devices. MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and may only be written by the CPU. Freescale Semiconductor, Inc... WOMQ — Wired-OR Mode for QSPI Pins 0 = Outputs have normal MOS drivers.
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Freescale Semiconductor, Inc. SPBR — Serial Clock Baud Rate The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is selected by writing a value from 2 to 255 into the SPBR field. The following equation determines the SCK baud rate: SCK Baud Rate = System Clock/(2SPBR) or SPBR = System Clock/(2SCK)(Baud Rate Desired) where SPBR equals {2, 3, 4,..., 255} Giving SPBR a value of zero or one disables the baud rate generator.
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Freescale Semiconductor, Inc. SPCR2 — QSPI Control Register 2 15 14 13 12 SPIFIE WREN WRTO 0 0 0 0 $YFFC1C 11 8 ENDQP 7 6 5 4 0 0 0 0 0 0 0 0 3 0 NEWQP RESET: 0 0 0 0 0 0 0 0 0 SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM has read access only. Writes to SPCR2 are buffered.
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Freescale Semiconductor, Inc. HALT — Halt 0 = Halt not enabled 1 = Halt enabled When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can later be restarted. SPSR — QSPI Status Register 15 $YFFC1F 8 SPCR3 7 SPIF 6 5 4 MODF HALTA 0 0 0 3 0 CPTQP RESET: 0 0 0 0 0 0 Freescale Semiconductor, Inc... SPSR contains QSPI status information. Only the QSPI can assert the bits in this register.
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Freescale Semiconductor, Inc. RR0 RR1 RR2 500 TR0 TR1 TR2 520 CR0 CR1 CR2 540 RECEIVE RAM TRANSMIT RAM COMMAND RAM RRD RRE RRF TRD TRE TRF CRD CRE CRF 51E 53E WORD 54F WORD BYTE Freescale Semiconductor, Inc... Figure 14 QSPI RAM Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate independently of the CPU.
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Freescale Semiconductor, Inc. Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options. A maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from the address in NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.) CONT — Continue 0 = Control of chip selects returned to PORTQS after transfer is complete.
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Freescale Semiconductor, Inc. 5.5.1 SCI Pins There are two unidirectional pins associated with the SCI. The SCI controls the transmit data (TXD) pin when enabled, whereas the receive data (RXD) pin remains a dedicated input pin to the SCI. TXD is available as a general-purpose I/O pin when the SCI transmitter is disabled. When used for I/O, TXD can be configured either as input or output, as determined by QSM register DDRQS. The following table shows SCI pins and their functions.
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Freescale Semiconductor, Inc. Table 25 SCI Baud Rates Freescale Semiconductor, Inc... Nominal Baud Rate Actual Rate with 16.78-MHz Clock 64.0 110.0 299.9 599.9 1199.7 2405.0 4810.0 9532.5 19418.1 37449.1 74898.3 524288.0 64* 110 300 600 1200 2400 4800 9600 19200 38400 76800 Maximum Rate SCBR Value Actual Rate with 20.97-MHz Clock — 110.0 300.1 600.1 1200.3 2400.6 4783.6 9637.6 19275.3 38550.6 72817.8 655360.
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Freescale Semiconductor, Inc. PT — Parity Type 0 = Even parity 1 = Odd parity When parity is enabled, PT determines whether parity is even or odd for both the receiver and the transmitter. Freescale Semiconductor, Inc... PE — Parity Enable 0 = SCI parity disabled 1 = SCI parity enabled PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the received parity bit is not correct, the SCI sets the PF error flag in SCSR.
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Freescale Semiconductor, Inc. RWU — Receiver Wakeup 0 = Normal receiver operation (received data recognized) 1 = Wakeup mode enabled (received data ignored until awakened) Setting RWU enables the wakeup function, which allows the SCI to ignore received data until awakened by either an idle line or address mark (as determined by WAKE). When in wakeup mode, the receiver status flags are not set, and interrupts are inhibited.
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Freescale Semiconductor, Inc. RAF — Receiver Active Flag 0 = SCI receiver is idle 1 = SCI receiver is busy RAF indicates whether the SCI receiver is busy. It is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in systems with multiple masters. Freescale Semiconductor, Inc... IDLE — Idle-Line Detected Flag 0 = SCI receiver did not detect an idle-line condition.
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Freescale Semiconductor, Inc. 6 General-Purpose Timer Module The 11-channel general-purpose timer (GPT) is used in systems where a moderate level of CPU control is required. The GPT consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators. A bus interface unit connects the GPT to the intermodule bus. IC1/PGP0 IC2/PGP1 IC3/PGP2 CAPTURE/COMPARE UNIT Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. PCLK PRESCALER – DIVIDE BY 4, 8, 16, 32, 64, 128, 256 SYSTEM CLOCK TCNT (HI) 1 OF 8 SELECT CPR2 CPR1 CPR0 TCNT (LO) TOI 16-BIT FREE RUNNING COUNTER TOF 9 INTERRUPT REQUESTS 16-BIT TIMER BUS IC1I 16-BIT LATCH CLK Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. SYSTEM CLOCK EXT. ÷512 ÷256 ÷512 ÷128 ÷64 ÷32 ÷16 ÷8 ÷4 ÷2 DIVIDER TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR CPR2 CPR1 CPR0 Freescale Semiconductor, Inc... ÷256 ÷128 ÷64 ÷32 ÷16 ÷8 ÷4 SELECT TO CAPTURE/ COMPARE TIMER EXT. ÷128 ÷64 ÷32 ÷16 ÷8 ÷4 ÷2 EXT.
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Freescale Semiconductor, Inc. PWMB REGISTER PWMABUF REGISTER PWMBBUF REGISTER "A" COMPARATOR "B" COMPARATOR PWMA PIN R LATCH S F1A BIT ZERO DETECTOR SFA BIT "A" MULTIPLEXER 16-BIT COUNTER R LATCH S PWMB PIN 8-BIT PWMA REGISTER 8-BIT Freescale Semiconductor, Inc... 16-BIT DATA BUS ZERO DETECTOR F1B BIT "B" MULTIPLEXER SFB BIT [14:0] FROM PRESCALER CLOCK 16/32 PWM BLOCK BLOCK Figure 18 PWM Unit Block Diagram 6.
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Freescale Semiconductor, Inc. 6.4 GPT Registers GPTMCR — GPT Module Configuration Register $YFF900 15 14 13 12 11 10 9 8 7 6 5 4 STOP FRZ1 FRZ0 STOPP INCP 0 0 0 SUPV 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 IARB RESET: 0 0 0 0 0 The GPTMCR contains parameters for configuring the GPT. STOP — Stop Clocks 0 = Internal clocks not shut down 1 = Internal clocks shut down Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. DDRGP/PORTGP — Port GP Data Direction Register/Port GP Data Register 15 DDGP7 14 13 12 11 10 9 8 DDGP6 DDGP5 DDGP4 DDGP3 DDGP2 DDGP1 DDGP0 $YFF906 7 6 5 4 3 2 1 0 PGP7 PGP6 PGP5 PGP4 PGP3 PGP2 PGP1 PGP0 0 0 0 0 0 0 0 0 RESET: 0 0 0 0 0 0 0 0 When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and PORTGP holds the 8-bit data.
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Freescale Semiconductor, Inc. PAMOD — Pulse Accumulator Mode 0 = External event counting 1 = Gated time accumulation PEDGE — Pulse Accumulator Edge Control The effects of PEDGE and PAMOD are shown in the following table. PAMOD 0 0 1 1 PEDGE 0 1 0 1 Effect PAI falling edge increments counter PAI rising edge increments counter Zero on PAI inhibits counting One on PAI inhibits counting Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits Each pair of bits specifies an action to be taken when output comparison is successful. OM/OL[5:2] 00 01 10 11 Action Taken Timer Disconnected from Output Logic Toggle OCx Output Line Clear OCx Output Line to 0 Set OCx Output Line to 1 Freescale Semiconductor, Inc... EDGE[4:1] — Input Capture Edge Control Bits Each pair of bits configures input sensing logic for the corresponding input capture.
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Freescale Semiconductor, Inc. CPR[2:0] — Timer Prescaler/PCLK Select Field This field selects one of seven prescaler taps or PCLK to be TCNT input. CPR[2:0] System Clock Divide-By Factor 4 8 16 32 64 128 256 PCLK 000 001 010 011 100 101 110 111 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. FOC[5:1] — Force Output Compare 0 = Has no meaning 1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set. FOC[5:1] correspond to OC[5:1]. FPWMA — Force PWMA Value 0 = Normal PWMA operation 1 = The value of F1A is driven out on the PWMA pin, regardless of the state of PPROUT. FPWMB — Force PWMB Value 0 = Normal PWMB operation 1 = The value of F1B is driven out on the PWMB pin. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. F1B — Force Logic Level One on PWMB 0 = Force logic level zero output on PWMB pin 1 = Force logic level one output on PWMB pin PWMA/PWMB — PWM Control Registers A/B $YFF926, $YFF927 These registers are associated with the pulse-width value of the PWM output on the corresponding PWM pin. A value of $00 loaded into one of these registers results in a continuously low output on the corresponding pin. A value of $80 results in a 50% duty cycle output.
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Freescale Semiconductor, Inc. 7 Summary of Changes Freescale Semiconductor, Inc... This is a complete revision, with complete reprint. All known errors in the publication have been corrected. The following summary lists significant changes. Typographical errors that do not affect content are not annotated. 82 Page 2 Revised ordering information. Page 5 New block diagram drawn. Page 6 New 132-pin assignment diagram drawn. Page 7 New 144-pin assignment diagram drawn. Page 8 New address map drawn.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68331TS/D For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.