Datasheet

March 20, 1997 5:12 pm Page 9 of 13
MC68302 Document
134 174 CS negated to address, FC invalid tcsnafi 12 - 135 175 CS low time (0 wait states) tcslt 60 - 136 176 CS negate to RW invalid tcsnrwi 7 - 137 177 CS assert to RW low (Write) tcsarwl - 8 138 178 CS negate to data in invalid tcsndii 0 - 139 180 Input data setup time tdsu 14 - 140 181 input data hold time tdh - 19 141 182 Clock high to data out valid tchdov - 20 142 190 Interrupt Pulse Width low IRQ tipw 28 - 143 191 Minimum time between active edges taemt 3 clks - 144 200 Timer input capture pulse width ttpw 28 - 145 201 TIN clock low pulse width tticlt 28 - 146 202 TIN clock high pulse width and input capture high
pulse width
tticht 2 clks -
147 203 TIN clock cycle time tcyc 3 clks - 148 204 Clock high to TOUT valid tchtov - 24 149 205 FRZ input setup time (to clock high) tfrzsu 14 - 150 206 FRZ input setup time (from clock high) tfrzht 7 -
Table 1:
#
Spec
No.
Description
Spec Name
UM
33MHz
Min
33MHz
Max
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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