Datasheet

March 20, 1997 5:12 pm
Page 3 of 13
MC68302 Document
34 37 BGACK assert to BG negate tgalgh
2.5 clks
4.5 clks
35 37A BGACK assert to BR negate tgalbrh
10 ns
1.5 clks
36 38 BG assert to Addr, Data, etc. hi-z tglz
-
25
37 39 BG width negate tgh
1.5 clks
-
38 40 BGACK assert to Address valid tgalav
15
-
39 41 BGACK assert to AS assert tgalasa
-
20
40 44 AS, DS negate to AVEC negate tshvph
0
25
41 46 BGACK width low tgal
1.5 clks
1.5 clks
42 47 Async input setup time tasi
7
-
43 48 BERR assert to DTACK assert tbeldal
7
-
44 53 Data-out hold from clk high tchdoi
0
-
45 55 R/W assert to Data bus impedance change trldbd
0
-
46 56 HALT/RESET pulse width thrpw
10 clks
-
47 57 BGACK negate to AS, DS, RW driven tgasd
1.5 clks
-
48 57A BGACK negate to FC tgafd
1 clk
-
49 58 BR negate to AS, DS, RW driven trhsd
1.5 clks
-
50 58A BR negate to FC trhfd
1 clk
Table 1:
#
Spec
No.
Description
Spec Name
UM
33MHz
Min
33MHz
Max
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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