Datasheet

March 20, 1997 5:12 pm Page 13 of 13
MC68302 Document
201 309 L1RXD hold time (from L1CLK falling edge) 26 - 202 315 RCLK1 and TCLK1 frequency Internal clk
External clk
- -
11 MHz
13.2 MHz
203 316 RCLK1 and TCLK1 low Internal clk
External clk
35ns
P+10
- -
204 316A RCLK1 and TCLK1 high Internal clk
External clk
35 25
- -
205 317 RCLK1 and TCLK1 rise/fall time Internal clk
External clk
- -
11
-
206 318 RXD1 active delay from TCLK1 falling edge Internal clk
External clk
0 0
20 30
207 319 RTS1 active/inactive delay from TCLK1 falling
edge
Internal clk External clk
0 0
20 50
208 320 CTS1 setup time to TCLK1 rising edge Internal clk
External clk
30
7
- -
209 321 RXD1 setup time to RCLK1 rising edge Internal clk
External clk
30
7
- -
210 322 RXD1 hold time from RCLK1 rising edge Internal clk
External clk
7
30
- -
211 323 CD1 setup time to RCLK1 rising edge Internal clk
External clk
30
7
- -
Table 1:
#
Spec
No.
Description
Spec Name
UM
33MHz
Min
33MHz
Max
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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