Datasheet

March 20, 1997 5:12 pm Page 12 of 13
MC68302 Document
185 288 L1RXD hold time from L1CLK rising edge 26 - 186 289 Time between successive L1SY1 64 L1CLK
192 L1CLK
- -
187 290 SDS1-SDS2 active delay from L1CLK rising edge 7 45 188 291 SDS1-SDS2 active delay from L1SY1 rising edge 7 45 189 292 SDS1-SDS2 inactive delay from L1CLK falling
edge
7 45
190 293 GCIDCL (GCI data clock) active delay 0 26 191 300 L1CLK (PCM clock) frequency - 13.2 MHz 192 301 L1CLK width low 27 - 193 301A L1CLK width high P+10 - 194 302 L1SY0-L1SY1 setup time 0 - 195 303 L1SY0-L1SY1 hold time 20 - 196 304 L1SY0-L1SY1 width low 1 L1CLK - 197 305 Time between successive sync signals 8 L1CLK - 198 306 L1TXD data valid after L1CLK rising edge 0 40 199 307 L1TXD to hi-z (from L1CLK rising edge) 0 26 200 308 L1RXD setup time (to L1CLK falling edge) 11 -
Table 1:
#
Spec
No.
Description
Spec Name
UM
33MHz
Min
33MHz
Max
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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