Datasheet

March 20, 1997 5:12 pm

Page 11 of 13

MC68302 Document

168 272 L1RQ valid before falling edge of L1SY1 1 L1CLKS -

169 273 L1GR setup time (to L1SY1 falling edge) 26 -

170 274 L1GR hold time (from L1SY1 falling edge) 26 -

171 275 SDS1-SDS2 active delay from L1CLK rising edge 7 40

172 276 SDS1-SDS2 inactive delay from L1CLK falling

edge

7 40

173 280 L1CLK clock period normal mode 1800 2100

174 281 L1CLK width low/high normal mode 840 1450

175 282 L1CLK rise/fall time Normal mode - -

176 280 L1CLK clock period MUX mode 150 -

177 281 L1CLK width low/high MUX mode 55 -

178 281A L1CLK width high MUX mode P+10 -

179 282 L1CLK rise/fall time MUX mode - -

180 283 L1SY1 sync setup time to L1CLK falling edge 15 -

181 284 L1SY1 sync hold time (from L1CLK falling edge) 26 -

182 285 L1TxD active delay (from L1ClK rising edge) 0 55

183 286 L1TXD active delay (from L1SY1 rising edge) 0 55

184 287 L1RXD Setup time to L1CLK rising edge 14 -

Table 1:

Spec

No.

Description

Spec Name

33MHz

Min

33MHz

Max

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...