Datasheet

March 20, 1997 5:12 pm Page 10 of 13
MC68302 Document
151 250 SPCLK clock output period 4 clks 64 clks 152 251 SPCLK clock output rise/fall time 0 6 153 252 Delay from SPCLK to transmit 0 20 154 253 SCP receive setup time 20 - 155 254 SCP receive hold time 6 - 156 260 L1CLK (IDL Clock) frequency - 13.3 MHz 157 261 L1CLK width low 28 - 158 262 L1CLK width high P+10 - 159 263 L1TXD, L1RQ, SDS1-SDS2 rise/fall time - 12 160 264 L1SY1 (sync) setup time (to L1CLK falling edge) 15 - 161 265 L1SY1 (sync) hold time (to L1CLK falling edge) 28 - 162 266 L1SY1 (sync) inactive before 4th L1CLK 0 - 163 267 L1TXD active delay (from L1CLK falling edge) 0 40 164 268 L1TXD to hi-z (from L1CLK rising edge) 0 26 165 269 L1RXD setup time (to L1CLK falling edge) 26 - 166 270 L1RXD hold time (from L1CLK falling edge) 26 - 167 271 Time between successive IDL syncs 20 L1CLKS -
Table 1:
#
Spec
No.
Description
Spec Name
UM
33MHz
Min
33MHz
Max
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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