Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) M683xx 8/16-Bit Single-Core 33 MHz

March 20, 1997 5:12 pm

Page 1 of 13

MC68302 Document

Table 1:

Spec

No.

Description

Spec Name

33MHz

Min

33MHz

Max

1 1 Cycle period tcyc

2 2,3 Clock pulse width tcl,tch

3 5A EXTAL to Clock delay tcd

4 6 Clock high to FC, address valid tchfcadv

5 7 Clock high to Address, Data Hi-z tchadz

6 8 Clock high to Address, FC invalid (Minimum) tchaﬁ

7 9 Clock high to AS, DS asserted tchsl

8 11 Address, FC Valid to AS, DS Assert (read)

AS assert (Write)

tafcvsl

9 12 Clock low to AS, DS negate tclsn

10 13 AS, DS Negated to Address FC Invalid tshaﬁ

11 14 AS (and DS read) width asserted tsl

12 14A DS width asserted, write tdsl

13 15 AS, DS width negate tsh

14 16 Clock high to Control Bus Hi-z tchca

15 17 AS, DS Negated to R/W Invalid tshrh

16 18 Clock high to R/W hi tchrh

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

Summary of content (13 pages)

PAGE 1
March 20, 1997 5:12 pm 2 1 5A 2,3 1 Clock high to FC, address valid EXTAL to Clock delay Clock pulse width Cycle period tchadz tchfcadv tcd tcl,tch tcyc 0 - 0 2 15 30 15 - 25 27 11 Table 1: 3 6 Clock high to Address, Data Hi-z tchafi 3 - 33MHz Max 4 7 Clock high to Address, FC invalid (Minimum) tchsl 8 15 33MHz Min 5 8 Clock high to AS, DS asserted tafcvsl - Spec Name UM 6 9 Address, FC Valid to AS, DS Assert (read) AS assert (Write) tclsn Description 7 11 Cloc
PAGE 2
March 20, 1997 5:12 pm 27 26 25 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 23 22 21 20A 20 HALT,RESET in transition time DTACK assert to Data-In valid AS, DS negated to BERR negated AS, DS Negated to Data In invalid AS, DS negate to DTACK negate Data in to Clock low Data-out valid to DS Asserted (Write) AS, DS Negated to Data-out invalid Clock low to data valid R/W low to DS assert (write) Address FC Valid to R/W Low (Write) AS Asserted to R/W Low (Write) Clock high to
PAGE 3
March 20, 1997 5:12 pm 46 45 44 43 42 41 40 39 38 37 36 35 34 57 56 55 53 48 47 46 44 41 40 39 38 37A 37 BGACK negate to FC BGACK negate to AS, DS, RW driven HALT/RESET pulse width R/W assert to Data bus impedance change Data-out hold from clk high BERR assert to DTACK assert Async input setup time BGACK width low AS, DS negate to AVEC negate BGACK assert to AS assert BGACK assert to Address valid BG width negate BG assert to Addr, Data, etc.
PAGE 4
March 20, 1997 5:12 pm 57 56 55 54 53 52 51 82 81 80 64 63 62 61 60 Clock high to BR low DREQ low to BR low DREQ width low DREQ asynchronous set up time RMC negate to BG assert Clock high to RMC negate Clock low to RMC assert Clock high to BCLRO hi-z Clock high to BCLR assert tchbrz tchbrl treqlbrl treql treqasi trmhgl tchrmh tclrml tchbcn tchbca 15 - - - 2 clks 10 - - - - - 33MHz Min 15 - 15 15 2 clks - - 15 17 17 15 15 33MHz Max Table 1: 58 83 C
PAGE 5
March 20, 1997 5:12 pm 72 71 70 69 68 67 97 96 95 94 93 92 91 90 RW valid to DS low DONE input low to clock high Clock low to DONE hi-z Clock high to DONE low (output) Clock low to DACK high Clock high to DACK low Clock low to BGACK hi-z Clock high to BGACK high Clock on which BGACK low to clock on which AS low tdsldiv trwvdsl tdnltch tcldnz tchdnl tclackh tchackl tclbkz tchbkh tclbklal Spec Name UM 0 - 0 10 - - - - - - 2 clks 33MHz Min - - 15 - - 15 15
PAGE 6
95 94 93 92 91 90 89 88 87 86 85 84 83 # 121 120 119 118 117 116 115 114 113 112 111 110 109A 108A Spec No.
PAGE 7
March 20, 1997 5:12 pm 110 109 108 107 106 105 104 103 102 101 100 144 143 142 141 140 131 130 129 128 127 126 125 AS high to data out hold time Clock high to data out valid Clock low to DTACK high Clock high to DTACK low Clock low to IAC low Clock high to IAC high Clock low to data in hold time Data in valid to clock low UDS/LDS inactive time AS high to address hold time on read AS high to data out hold time AS high to data hi-z Clock high to data out valid tchcsiakl t
PAGE 8
March 20, 1997 5:12 pm 128 127 126 125 124 123 122 121 120 119 118 117 168 167 165 164 163 162 161 160 158 157 156 155 154 AS high to BERR hi-z AS low to BERR low AS high to DTACK high AS low to DTACK low (0 wait states) AS negated to address hold time RW valid to AS low Address valid to AS low AS high to CS high AS low to CS low DTACK high to DTACK hi-z Clock low to BERR hi-z Clock high to BERR low Clock low to DTACK high Clock low to DTACK low (1-6 wait states) tidh
PAGE 9
March 20, 1997 5:12 pm 145 144 143 142 141 140 139 138 137 136 135 134 202 201 200 191 190 182 181 180 178 177 176 175 174 TIN clock cycle time TIN clock high pulse width and input capture high pulse width TIN clock low pulse width Timer input capture pulse width Minimum time between active edges Interrupt Pulse Width low IRQ Clock high to data out valid input data hold time Input data setup time CS negate to data in invalid CS assert to RW low (Write) CS negate to RW in
PAGE 10
March 20, 1997 5:12 pm 159 158 157 156 155 154 153 152 151 264 263 262 261 260 254 253 252 251 250 L1SY1 (sync) hold time (to L1CLK falling edge) L1SY1 (sync) setup time (to L1CLK falling edge) L1TXD, L1RQ, SDS1-SDS2 rise/fall time L1CLK width high L1CLK width low L1CLK (IDL Clock) frequency SCP receive hold time SCP receive setup time Delay from SPCLK to transmit SPCLK clock output rise/fall time SPCLK clock output period 0 28 15 - P+10 28 - 6 20 0 0 4 clks 33MHz
PAGE 11
March 20, 1997 5:12 pm 172 171 170 169 168 280 276 275 274 273 272 L1CLK width low/high normal mode L1CLK clock period normal mode SDS1-SDS2 inactive delay from L1CLK falling edge SDS1-SDS2 active delay from L1CLK rising edge L1GR hold time (from L1SY1 falling edge) L1GR setup time (to L1SY1 falling edge) L1RQ valid before falling edge of L1SY1 - 840 1800 7 7 26 26 1 L1CLKS 33MHz Min - - 1450 2100 40 40 - - - 33MHz Max Table 1: 173 281 L1CLK rise/fall time Normal mode
PAGE 12
March 20, 1997 5:12 pm 195 194 193 192 191 190 189 188 187 186 185 304 303 302 301A 301 300 293 292 291 290 289 288 Time between successive sync signals L1SY0-L1SY1 width low L1SY0-L1SY1 hold time L1SY0-L1SY1 setup time L1CLK width high L1CLK width low L1CLK (PCM clock) frequency GCIDCL (GCI data clock) active delay SDS1-SDS2 inactive delay from L1CLK falling edge SDS1-SDS2 active delay from L1SY1 rising edge SDS1-SDS2 active delay from L1CLK rising edge Time between succe
PAGE 13
March 20, 1997 5:12 pm 201 315 309 RCLK1 and TCLK1 low RCLK1 and TCLK1 frequency L1RXD hold time (from L1CLK falling edge) Internal clk External clk Internal clk External clk Internal clk External clk - 35 25 35ns P+10 - 26 33MHz Min 20 30 11 - - - 11 MHz 13.