Datasheet

Register Descriptions
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 79
Preliminary
5.6.18.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.19 IRQ Pending 1 Register (IRQP1)
Figure 5-21 IRQ Pending 1 Register (IRQP1)
5.6.19.1 IRQ Pending (PENDING)—Bits 32–17
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.20 IRQ Pending 2 Register (IRQP2)
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1 IRQ Pending (PENDING)—Bits 48–33
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.21 IRQ Pending 3 Register (IRQP3)
Figure 5-23 IRQ Pending 3 Register (IRQP3)
$Base + $12
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING [32:17]
Write
RESET
1111111111111111
Base + $13
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING [48:33]
Write
RESET
1111111111111111
Base + $14
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING [64:49]
Write
RESET
1111111111111111