Datasheet

56F8323 Technical Data, Rev. 17

76 Freescale Semiconductor

Preliminary

5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)—

Bits 12–0

The contents of this register determine the location of the Vector Address Table. The value in this register

is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are

determined based upon the highest-priority interrupt; see Part 5.3.1 for details.

5.6.12 Fast Interrupt 0 Match Register (FIM0)

Figure 5-14 Fast Interrupt 0 Match Register (FIM0)

5.6.12.1 Reserved—Bits 15–7

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0

This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first; for details, see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected

results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become

the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being

declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector

number of each IRQ, refer to Table 4-3.

5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

Base + $B

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

0 0 0 0 0 0 0 0 0

FAST INTERRUPT 0

Write

RESET

0000000000000000