Datasheet

56F8323 Technical Data, Rev. 17
72 Freescale Semiconductor
Preliminary
5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.9 Interrupt Priority Register 8 (IPR8)
Figure 5-11 Interrupt Priority Register 8 (IPR8)
5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0 RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0 RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
Base + $8
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
SCI0_RCV
IPL
SCI0_RERR
IPL
0 0
SCI0_TIDL
IPL
SCI0_XMIT
IPL
TMRA3 IPL TMRA2 IPL TMRA1 IPL
Write
RESET
0000000000000000