Datasheet

56F8323 Technical Data, Rev. 17
60 Freescale Semiconductor
Preliminary
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00 F1A0)
Register Acronym Base Address + Register Name Section Location
IPR0 $0
Interrupt Priority Register 0
5.6.1
IPR1 $1
Interrupt Priority Register 1
5.6.2
IPR2 $2
Interrupt Priority Register 2
5.6.3
IPR3 $3
Interrupt Priority Register 3
5.6.4
IPR4 $4
Interrupt Priority Register 4
5.6.5
IPR5 $5
Interrupt Priority Register 5
5.6.6
IPR6 $6
Interrupt Priority Register 6
5.6.7
IPR7 $7
Interrupt Priority Register 7
5.6.8
IPR8 $8
Interrupt Priority Register 8
5.6.9
IPR9 $9
Interrupt Priority Register 9
5.6.10
VBA $A
Vector Base Address Register
5.6.11
FIM0 $B
Fast Interrupt 0 Match Register
5.6.12
FIVAL0 $C
Fast Interrupt 0 Vector Address Low Register
5.6.13
FIVAH0 $D
Fast Interrupt 0 Vector Address High Register
5.6.14
FIM1 $E
Fast Interrupt 1 Match Register
5.6.15
FIVAL1 $F
Fast Interrupt 1 Vector Address Low Register
5.6.16
FIVAH1 $10
Fast Interrupt 1 Vector Address High Register
5.6.17
IRQP0 $11
IRQ Pending Register 0
5.6.18
IRQP1 $12
IRQ Pending Register 1
5.6.19
IRQP2 $13
IRQ Pending Register 2
5.6.20
IRQP3 $14
IRQ Pending Register 3
5.6.21
IRQP4 $15
IRQ Pending Register 4
5.6.22
IRQP5 $16
IRQ Pending Register 5
5.6.23
Reserved
ICTL $1D
Interrupt Control Register
5.6.30