Datasheet

56F8323 Technical Data, Rev. 17

52 Freescale Semiconductor

Preliminary

Table 4-27 FlexCAN Registers Address Map

(FC_BASE = $00 F800)

FlexCAN is NOT available in the 56F8123 device

FCMCR $0 Module Configuration Register

Reserved

FCCTL0 $3 Control Register 0 Register

FCCTL1 $4 Control Register 1 Register

FCTMR $5 Free-Running Timer Register

FCMAXMB $6 Maximum Message Buffer Configuration Register

Reserved

FCRXGMASK_H $8 Receive Global Mask High Register

FCRXGMASK_L $9 Receive Global Mask Low Register

FCRX14MASK_H $A Receive Buffer 14 Mask High Register

FCRX14MASK_L $B Receive Buffer 14 Mask Low Register

FCRX15MASK_H $C Receive Buffer 15 Mask High Register

FCRX15MASK_L $D Receive Buffer 15 Mask Low Register

Reserved

FCSTATUS $10 Error and Status Register

FCIMASK1 $11 Interrupt Masks 1 Register

FCIFLAG1 $12 Interrupt Flags 1 Register

FCR/T_ERROR_CNTRS $13 Receive and Transmit Error Counters Register

Reserved

FCMB0_CONTROL $40 Message Buffer 0 Control / Status Register

FCMB0_ID_HIGH $41 Message Buffer 0 ID High Register

FCMB0_ID_LOW $42 Message Buffer 0 ID Low Register

FCMB0_DATA $43 Message Buffer 0 Data Register

FCMB0_DATA $44 Message Buffer 0 Data Register

FCMB0_DATA $45 Message Buffer 0 Data Register

FCMB0_DATA $46 Message Buffer 0 Data Register

Reserved

FCMSB1_CONTROL $48 Message Buffer 1 Control / Status Register

FCMSB1_ID_HIGH $49 Message Buffer 1 ID High Register

FCMSB1_ID_LOW $4A Message Buffer 1 ID Low Register