Datasheet

Peripheral Memory Mapped Registers

56F8323 Technical Data, Rev. 17

Freescale Semiconductor 49

Preliminary

Table 4-21 GPIOA Registers Address Map

(GPIOA_BASE = $00 F2E0)

Address Offset Register Description Reset Value

GPIOA_PUR $0 Pull-up Enable Register 0 x 0FFF

GPIOA_DR $1 Data Register 0 x 0000

GPIOA_DDR $2 Data Direction Register 0 x 0000

GPIOA_PER $3 Peripheral Enable Register 0 x 0FFF

GPIOA_IAR $4 Interrupt Assert Register 0 x 0000

GPIOA_IENR $5 Interrupt Enable Register 0 x 0000

GPIOA_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOA_IPR $7 Interrupt Pending Register 0 x 0000

GPIOA_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 0FFF

GPIOA_RAWDATA $A Raw Data Input Register —

Table 4-22 GPIOB Registers Address Map

(GPIOB_BASE = $00 F300)

GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF

GPIOB_DR $1 Data Register 0 x 0000

GPIOB_DDR $2 Data Direction Register 0 x 0000

GPIOB_PER $3 Peripheral Enable Register 0 x 00FF

GPIOB_IAR $4 Interrupt Assert Register 0 x 0000

GPIOB_IENR $5 Interrupt Enable Register 0 x 0000

GPIOB_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOB_IPR $7 Interrupt Pending Register 0 x 0000

GPIOB_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOB_PPMODE $9 Push-Pull Mode Register 0 x 00FF

GPIOB_RAWDATA $A Raw Data Input Register —