Datasheet

56F8323 Technical Data, Rev. 17

48 Freescale Semiconductor

Preliminary

Table 4-17 Serial Peripheral Interface 0 Registers Address Map

(SPI0_BASE = $00 F2A0)

SPI0_SPSCR $0 Status and Control Register

SPI0_SPDSR $1 Data Size Register

SPI0_SPDRR $2 Data Receive Register

SPI0_SPDTR $3 Data Transmitter Register

Table 4-18 Serial Peripheral Interface 1 Registers Address Map

(SPI1_BASE = $00 F2B0)

SPI1_SPSCR $0 Status and Control Register

SPI1_SPDSR $1 Data Size Register

SPI1_SPDRR $2 Data Receive Register

SPI1_SPDTR $3 Data Transmitter Register

Table 4-19 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F2C0)

COPCTL $0 Control Register

COPTO $1 Time-Out Register

COPCTR $2 Counter Register

Table 4-20 Clock Generation Module Registers Address Map

(CLKGEN_BASE = $00 F2D0)

PLLCR $0 Control Register

PLLDB $1 Divide-By Register

PLLSR $2 Status Register

Reserved

SHUTDOWN $4 Shutdown Register

OSCTL $5 Oscillator Control Register