Datasheet

Peripheral Memory Mapped Registers

56F8323 Technical Data, Rev. 17

Freescale Semiconductor 43

Preliminary

TMRC1_HOLD $14 Hold Register

TMRC1_CNTR $15 Counter Register

TMRC1_CTRL $16 Control Register

TMRC1_SCR $17 Status and Control Register

TMRC1_CMPLD1 $18 Comparator Load Register 1

TMRC1_CMPLD2 $19 Comparator Load Register 2

TMRC1_COMSCR $1A Comparator Status and Control Register

Reserved

TMRC2_CMP1 $20 Compare Register 1

TMRC2_CMP2 $21 Compare Register 2

TMRC2_CAP $22 Capture Register

TMRC2_LOAD $23 Load Register

TMRC2_HOLD $24 Hold Register

TMRC2_CNTR $25 Counter Register

TMRC2_CTRL $26 Control Register

TMRC2_SCR $27 Status and Control Register

TMRC2_CMPLD1 $28 Comparator Load Register 1

TMRC2_CMPLD2 $29 Comparator Load Register 2

TMRC2_COMSCR $2A Comparator Status and Control Register

Reserved

TMRC3_CMP1 $30 Compare Register 1

TMRC3_CMP2 $31 Compare Register 2

TMRC3_CAP $32 Capture Register

TMRC3_LOAD $33 Load Register

TMRC3_HOLD $34 Hold Register

TMRC3_CNTR $35 Counter Register

TMRC3_CTRL $36 Control Register

TMRC3_SCR $37 Status and Control Register

TMRC3_CMPLD1 $38 Comparator Load Register 1

TMRC3_CMPLD2 $39 Comparator Load Register 2

TMRC3_COMSCR $3A Comparator Status and Control Register

Table 4-9 Quad Timer C Registers Address Map (Continued)

(TMRC_BASE = $00 F0C0)