Datasheet

Signal Pins
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 29
Preliminary
TC0
(TXD0)
(GPIOC6)
1Schmitt
Input/
Output
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
TC0 — Timer C, Channel 0
Transmit Data — SCI0 transmit data output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC0.
TC1
(RXD0)
(GPIOC5)
64 Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
TC1 — Timer C, Channel 1
Receive Data — SCI0 receive data input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC1.
TC3
(GPIOC4)
63 Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
TC3 — Timer C Channel 3
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC3.
IRQA
(V
PP
)
12 Schmitt
Input
Input
Input,
pull-up
enabled
External Interrupt Request A — The IRQA
input is an
asynchronous external interrupt request during Stop and Wait mode
operation. During other operating modes, it is a synchronized
external interrupt request which indicates an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered
V
PP
— This pin is used for Flash debugging purposes.
RESET
2Schmitt
Input
Input,
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET
is asserted low, the device is initialized and placed in
the reset state. A Schmitt trigger input is used for noise immunity.
The internal reset signal will be deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
To ensure complete hardware reset, RESET
and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert RESET
,
but do not assert TRST
.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No. Type
State During
Reset
Signal Description