Datasheet

Signal Pins
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 23
Preliminary
HOME0
(TA3)
(GPIOB4)
(prescaler_
clock)
49 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
Input,
pull-up
enabled
Home — Quadrature Decoder 0, HOME input
TA3 — Timer A, Channel 3
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Clock Output - can be used to monitor the internal prescaler_clock
signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is HOME0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
SCLK0
(GPIOB3)
25 Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCLK0.
MOSI0
(GPIOB2)
24 Schmitt
Input/
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
SPI 0 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MOSI0.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No. Type
State During
Reset
Signal Description