Datasheet

56F8323 Technical Data, Rev. 17
22 Freescale Semiconductor
Preliminary
PHASEB0
(TA1)
(GPIOB6)
(SYS_CLK2)
51 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
Input,
pull-up
enabled
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A ,Channel 1
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK2
signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is PHASEB0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
INDEX0
(TA2)
(GPIOB5)
(SYS_CLK)
50 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
Input,
pull-up
enabled
Index — Quadrature Decoder 0, INDEX input
TA2 — Timer A, Channel 2
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK signal
(see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is INDEX0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No. Type
State During
Reset
Signal Description