Datasheet

Signal Pins
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 21
Preliminary
TMS 54 Schmitt
Input
Input,
pulled high
internally
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note: Always tie the TMS pin to V
DD
through a 2.2K resistor.
TDI 55 Schmitt
Input
Input,
pulled high
internally
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
TDO 56 Output In reset,
output is
disabled,
pull-up is
enabled
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
TRST
58 Schmitt
Input
Input,
pulled high
internally
Test Reset — As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment when a hardware
device reset is required and the EOnCE/JTAG module must not be
reset. In this case, assert RESET
, but do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note: For normal operation, connect TRST
directly to V
SS
. If the design
is to be used in a debugging environment, TRST
may be tied to V
SS
through
a 1K resistor.
PHASEA0
(TA0)
(GPIOB7)
(oscillator_
clock)
52 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Clock Output - can be used to monitor the internal oscillator clock
signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8323, the default state after reset is PHASEA0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No. Type
State During
Reset
Signal Description