Datasheet

56F8323 Technical Data, Rev. 17
20 Freescale Semiconductor
Preliminary
V
CAP
1 57 Supply Supply V
CAP
1 - 4 — When OCR_DIS is tied to V
SS
(regulator enabled),
connect each pin to a 2.2μF or greater bypass capacitor in order to
bypass the core logic voltage regulator, required for proper chip
operation.
When OCR_DIS is tied to V
DD
, (regulator disabled), these pins
become V
DD_CORE
and should be connected to a regulated 2.5V
power supply.
Note: This bypass is required even if the chip is powered with
an external supply.
V
CAP
2 23
V
CAP
3 5
V
CAP
4 43
OCR_DIS 45 On-Chip Regulator Disable —
Tie this pin to V
SS
to enable the on-chip regulator
Tie this pin to V
DD
to disable the on-chip regulator
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
EXTAL
(GPIOC0)
46 Input
Schmitt
Input/
Output
Input External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to V
SS
.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an EXTAL input with pull-ups disabled.
XTAL
(GPIOC1)
47 Output
Schmitt
Input/
Output
Output Crystal Oscillator Output — This output can be connected to an
8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to V
SS
.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an XTAL input with pull-ups disabled.
TCK 53 Schmitt
Input
Input,
pulled low
internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor. A Schmitt
trigger input is used for noise immunity.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No. Type
State During
Reset
Signal Description