Datasheet

56F8323 Technical Data, Rev. 17
16 Freescale Semiconductor
Preliminary
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8323 and 56F8123 are organized into functional groups, as
detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row
describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins in Package
56F8323 56F8123
Power (V
DD
or V
DDA
)66
Power Option Control 1 1
Ground (V
SS
or V
SSA
)55
Supply Capacitors
1
& V
PP
2
1. If the on-chip regulator is disabled, the V
CAP
pins serve as 2.5V V
DD_CORE
power inputs
2. The V
PP
input shares the IRQA input
44
PLL and Clock 2 2
Interrupt and Program Control 2 2
Pulse Width Modulator (PWM) Ports
3
3. Pins in this section can function as SPI #1 and GPIO
12 —
Serial Peripheral Interface (SPI) Port 0
4
4. Pins in this section can function as SCI #1 and GPIO
48
Quadrature Decoder Port 0
5
5. Alternately, can function as Quad Timer A pins or GPIO
4—
CAN Ports 2 —
Analog-to-Digital Converter (ADC) Ports 13 13
Timer Module Port C
6
6. Two pins can function as SCI #0 and GPIO
Note: See Table 1-1 for 56F8123 functional differences.
33
Timer Module Port A — 4
JTAG/Enhanced On-Chip Emulation (EOnCE) 5 5
Temperature Sensse 1 —
Dedicated GPIO — 10