Datasheet

Architecture Block Diagram
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 13
Preliminary
Figure 1-2 Peripheral Subsystem
IPBus
Timer A
SPI 0
ADCA
3
8
SPI 1
GPIO A
4
Interrupt
Controller
To/From IPBus Bridge
PWM A
SCI 0
8
System POR
Low-Voltage Interrupt
COP Reset
COP
RESET
Quadrature Decoder 0
4
GPIO B
GPIO C
FlexCAN
SCI 1
4
TEMP_SENSE
CLKGEN
(OSC/PLL)
(ROSC)
POR & LVI
SIM
2
ch2i
ch2o
Timer C
2
2
SYNC Output
NOT available on the 56F8123 device.