Datasheet

JTAG Timing
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 125
Preliminary
Figure 10-18 Test Clock Input Timing Diagram
Figure 10-19 Test Access Port Timing Diagram
Figure 10-20 TRST Timing Diagram
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
– V
IL
)/2
t
PW
1/f
OP
t
PW
V
M
V
IH
Input Data Valid
Output Data Valid
Output Data Valid
t
DS
t
DH
t
DV
t
TS
t
DV
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output
)
TDO
(Output)
TMS
TRST
(Input)
t
TRST