Datasheet

56F8323 Technical Data, Rev. 17
124 Freescale Semiconductor
Preliminary
10.13 Controller Area Network (CAN) Timing
Note: The CAN is NOT available in the 56F8123 device.
Figure 10-17 Bus Wakeup Detection
10.14 JTAG Timing
Table 10-22 CAN Timing
1
1. Parameters listed are guaranteed by design
Characteristic Symbol Min Max Unit See Figure
Baud Rate
BR
CAN
—
1 Mbps
—
Bus Wake-up detection
T
WAKEUP
T
IPBUS
—
μs 10-17
Table 10-23 JTAG Timing
Characteristic Symbol Min Max Unit See Figure
TCK frequency of operation using
EOnce
1
1. TCK frequency of operation must be less than 1/8 the processor rate.
f
OP
DC SYS_CLK/8 MHz 10-18
TCK frequency of operation not
using EOnce
1
f
OP
DC SYS_CLK/4 MHz 10-18
TCK clock pulse width
t
PW
50 — ns 10-18
TMS, TDI data set up time
t
DS
5—ns 10-19
TMS, TDI data hold time
t
DH
5—ns 10-19
TCK low to TDO data valid
t
DV
—30ns 10-19
TCK low to TDO tri-state
t
TS
—30ns 10-19
TRST
assertion time
t
TRST
2T
2
2. T = processor clock period (nominally 1/60MHz)
—ns 10-20
T
WAKEUP
MSCAN_RX
CAN receive
data pin
(Input)