Datasheet

56F8323 Technical Data, Rev. 17
12 Freescale Semiconductor
Preliminary
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
Note: The primary data RAM port is 32 bits wide. Other data ports are
16 bits.
56800E
Program
Flash
Program
RAM
Data RAM
Data Flash
IPBus
Bridge
Boot
Flash
Flash
Memory
Module
CHIP
TAP
Controller
TAP
Linking
Module
5
NOT available on the 56F8123 device.
To Flash
Control
Logic
JTAG / EOnCE
pdb_m[15:0]
pab[20:0]
cdbw[31:0]
xab1[23:0]
xab2[23:0]
cdbr_m[31:0]
xdb2_m[15:0]
IPBus
External
JTAG Port