Datasheet

56F8323 Technical Data, Rev. 17
118 Freescale Semiconductor
Preliminary
Figure 10-5 Asynchronous Reset Timing
Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive)
Figure 10-7 External Level-Sensitive Interrupt Timing
Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing
First Fetch
t
RA
t
RAZ
t
RDA
PAB
PDB
RESET
IRQA
t
IRW
t
IG
General
Purpose
I/O Pin
IRQA
b) General Purpose I/O
t
IDM
PAB
IRQA
a) First Interrupt Instruction Execution
First Interrupt Instruction Execution
Not IRQA Interrupt Vector
t
IW
IRQA
t
IF
First Instruction Fetch
PAB