Datasheet

Phase Locked Loop Timing
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 115
Preliminary
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
10.7 Crystal Oscillator Parameters
Table 10-14 PLL Timing
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8MHz input crystal.
f
osc
488.4MHz
PLL output frequency
2
(f
OUT
)—56F8323
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
OUT
/2), please refer to the OCCS chapter in
the 56F8300 Peripheral User Manual.
f
op
160 — 260 MHz
PLL output frequency
2
(f
OUT
)—56F8123
f
op
160 — 160 MHz
PLL stabilization time
3
-40° to +125°C
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
t
plls
—110ms
Table 10-15 Crystal Oscillator Parameters
Characteristic Symbol Min Typ Max Unit
Crystal Start-up time T
CS
4510ms
Resonator Start-up time T
RS
0.1 0.18 1 ms
Crystal ESR R
ESR
——120ohms
Crystal Peak-to-Peak Jitter T
D
70 — 250 ps
Crystal Min-Max Period Variation T
PV
0.12 — 1.5 ns
Resonator Peak-to-Peak Jitter T
RJ
——300ps
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
t
fall
t
rise