Datasheet

DC Electrical Characteristics
56F8323 Technical Data, Rev. 17
Freescale Semiconductor 111
Preliminary
10.2.1 Voltage Regulator Specifications
The 56F8323/56F8123 have two on-chip regulators. One supplies the PLL and has no external pins;
therefore, it has no external characteristics which must be guaranteed (other than proper operation of the
device). The second regulator supplies approximately 2.6V to the device’s core logic. This regulator
requires two external 2.2μF, or greater, capacitors for proper operation. Ceramic and tantalum capacitors
tend to provide better performance tolerances. The output voltage can be measured directly on the V
CAP
pins. The specifications for this regulator are shown in Table 10-9.
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
Mode
I
DD_Core
I
DD_IO
1
1. No Output Switching (Output switching current can be estimated from I = CVf for each output)
I
DD_ADC
I
DD_OSC_PLL
Test Conditions
RUN1_MAC
110mA 13μA25mA 2.5mA
• 60MHz Device Clock
• All peripheral clocks are enabled
• Continuous MAC instructions with
fetches from Data RAM
• ADC powered on and clocked
Wait3
55mA 13μA35μA2.5mA
• 60MHz Device Clock
• All peripheral clocks are enabled
• ADC powered off
Stop1
700μA13μA0μA360μA
• 4MHz Device Clock
• All peripheral clocks are off
• Relaxation oscillator is on
• ADC powered off
• PLL powered off
Stop2
100μA13μA0μA145μA
• Relaxation oscillator is off
• All peripheral clocks are off
• ADC powered off
• PLL powered off
Table 10-9. Regulator Parameters
Characteristic Symbol Min Typical Max Unit
Unloaded Output Voltage
(0mA Load)
V
RNL
2.25 — 2.75 V
Loaded Output Voltage
(200mA load)
V
RL
2.25 — 2.75 V
Line Regulation @ 250mA load
(V
DD
33 ranges from 3.0V to 3.6V)
V
R
2.25 — 2.75 V