Datasheet

56F8323 Technical Data, Rev. 17

104 Freescale Semiconductor

Preliminary

8.3 Memory Maps

The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based

on this and the default function of each of the GPIO pins, the reset values of the GPIOX_PUR and

GPIOX_PER registers change from port to port. Tables 4-21 through 4-23 define the actual reset values

of these registers.

Part 9 Joint Test Action Group (JTAG)

9.1 JTAG Information

Please contact your Freescale sales representative or authorized distributor for device/package-specific

BSDL information.

GPIOB7 PHASEA0 / TA0 52 Quad Decoder 0 register DECCR is used to select between

Decoder 0 and Timer A

Quad Decoder is NOT available in 56F8123

GPIOC0 EXTAL 46 Pull-ups default to disabled

GPIOC1 XTAL 47 Pull-ups default to disabled

GPIOC2 CAN_RX 61 CAN is NOT available in 56F8123

GPIOC3 CAN_TX 62 CAN is NOT available in 56F8123

GPIOC4 TC3 63

GPIOC5 TC1 / RXD0 64 SIM register SIM_GPS is used to select between Timer C and

SCI0 on a pin-by-pin basis

GPIOC6 TC0 / TXD0 1 SIM register SIM_GPS is used to select between Timer C and

SCI0 on a pin-by-pin basis

Table 8-3 GPIO External Signals Map (Continued)

GPIO Function

Peripheral

Function

Package

Notes