56F8323/56F8123 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8323 Rev. 17 04/2007 freescale.
Document Revision History Version History Description of Change Rev 1.0 Pre-Release version, Alpha customers only Rev 2.0 Initial Public Release Rev 3.0 Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues. Rev 4.0 Added Package Pins to GPIO Table in Section 8. Removed reference to pin group 9 in Table 10-5. Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling, consistency of language throughout family.
Document Revision History Version History Description of Change Rev 14.0 Added information/corrected state during reset in Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz. Rev 15.0 Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2. Rev. 16 • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor.
56F8323 Technical Data, Rev.
6F8323/56F8123 General Description Note: Features in italics are NOT available in the 56F8123 device.
Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 7 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8323/56F8123 Features . . . . . . . . . . . . . 7 Device Description . . . . . . . . . . . . . . . . . . . . 9 Award-Winning Development Environment 10 Architecture Block Diagram . . . . . . . . . . . . 11 Product Documentation . . . . . . . . . . . . . . . 15 Data Sheet Conventions . . . . . . . . . . . . . . . 15 Part 2: Signal/Connection Descriptions . . 16 2.1. Introduction . . . . . . .
56F8323/56F8123 Features Part 1 Overview 1.1 56F8323/56F8123 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
1.1.3 Memory Note: Features in italics are NOT available in the 56F8123 device. • • • Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection On-chip memory, including a low-cost, high-volume Flash solution — 32KB of Program Flash — 4KB of Program RAM — 8KB of Data Flash — 8KB of Data RAM — 8KB of Boot Flash • 1.1.4 EEPROM emulation capability Peripheral Circuits Note: Features in italics are NOT available in the 56F8123 device.
Device Description 1.1.5 • • • • • • Energy Information Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power 1.
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators.
Architecture Block Diagram 1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8123 device and are shaded in the following figures. The 56F8323/56F8123 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function.
5 JTAG / EOnCE Boot Flash pdb_m[15:0] CHIP TAP Controller TAP Linking Module pab[20:0] Program Flash cdbw[31:0] Program RAM 56800E xab1[23:0] Data RAM xab2[23:0] Data Flash External JTAG Port cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge NOT available on the 56F8123 device. To Flash Control Logic Flash Memory Module IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory (FM) Module.
Architecture Block Diagram To/From IPBus Bridge CLKGEN (OSC/PLL) Interrupt Controller (ROSC) Low-Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 RESET SIM COP Reset 2 4 FlexCAN 2 COP SPI 1 SCI 1 4 SPI 0 PWM A 8 SYNC Output GPIO A 2 SCI 0 GPIO B GPIO C ch2i 3 Timer C ch2o ADCA 8 TEMP_SENSE NOT available on the 56F8123 device. IPBus Figure 1-2 Peripheral Subsystem 56F8323 Technical Data, Rev.
Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
Product Documentation 1.5 Product Documentation The documents listed in Table 1-3 are required for a complete description and proper design with the 56F8323 and 56F8123 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com/semiconductors.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8323 and 56F8123 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row describes the signal or signals present on a pin.
Introduction Power VDD_IO Power VDDA_OSC_PLL Ground VSS Power Ground VDDA_ADC VSSA_ADC 4 1 1 1 4 1 1 1 PLL and Clock or GPIO VCAP1 - VCAP4 OCR_DIS EXTAL (GPIOC0) XTAL (GPIOC1) 4 1 1 1 56F8323 1 1 1 2 1 1 1 1 3 3 1 8 5 1 1 1 TCK JTAG/ EOnCE Port TMS TDI TDO TRST PHASEB0 (TA1, GPIOB6) INDEX0 (TA2, GPIOB5) HOME0 (TA3, GPIOB4) Quadrature Decoder 0 or Quad Timer A or GPIO 1 1 Other Supply Ports PHASEA0 (TA0, GPIOB7) 1 1 1 1 1 1 1 1 1 SCLK0 (GPIOB3) MOSI0 (GPIOB2) MISO0
Power VDD_IO Power VDDA_OSC_PLL Ground VSS Power Ground VDDA_ADC VSSA_ADC 4 1 1 1 4 1 1 1 PLL and Clock or GPIO VCAP1 - VCAP4 OCR_DIS EXTAL (GPIOC0) XTAL (GPIOC1) 4 1 1 1 56F8123 1 1 1 2 1 1 1 1 3 3 8 5 1 1 1 TCK JTAG/ EOnCE Port TMS TDI TDO TRST TA1 (GPIOB6) TA2 (GPIOB5) Quad Timer A or GPIO TA3 (GPIOB4) 1 1 Other Supply Ports TA0 (GPIOB7) 1 1 1 1 1 1 1 1 1 SCLK0 (GPIOB3) MOSI0 (GPIOB2) MISO0 (RXD1, GPIOB1) SPI0 or SCI1 or GPIO SS0 (TXD1, GPIOB0) GPIOA0-1 SS1
Signal Pins 2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). In the 56F8123, after reset, each pin must be configured for the desired function. The initialization software will configure each pin for the function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed. Note: Signals in italics are not available in the 56F8123 device.
Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type State During Reset VCAP1 57 Supply Supply VCAP2 23 VCAP3 5 VCAP4 43 Signal Description VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled), connect each pin to a 2.2μF or greater bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. When OCR_DIS is tied to VDD, (regulator disabled), these pins become VDD_CORE and should be connected to a regulated 2.
Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type TMS 54 Schmitt Input State During Reset Input, pulled high internally Signal Description Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.
Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type PHASEB0 51 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase B — Quadrature Decoder 0, PHASEB input (TA1) Schmitt Input/ Output TA1 — Timer A ,Channel 1 (GPIOB6) Schmitt Input/ Output Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SYS_CLK2) Output Clock Output - can be used to monitor the internal SYS_CLK2 signal (see Part 6.5.
Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type HOME0 49 Schmitt Input State During Reset Input, pull-up enabled Signal Description Home — Quadrature Decoder 0, HOME input (TA3) Schmitt Input/ Output TA3 — Timer A, Channel 3 (GPIOB4) Schmitt Input/ Output Port B GPIO — This GPIO pin can be individually programmed as an input or output pin.
Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type State During Reset MISO0 22 Schmitt Input/ Output Input, pull-up enabled Signal Description SPI 0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected.
Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type PWMA2 7 Output (SS1) Schmitt Input (GPIOA2) Schmitt Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description PWMA2 — This is one of six PWMA output pins. SPI 1 Slave Select — SS1 is used in slave mode to indicate to the SPI module that the current transfer is to be received.
Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type PWMA5 10 Output (SCLK1) Schmitt Input/ Output (GPIOA5) Schmitt Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description PWMA5 — This is one of six PWMA output pins. SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity.
Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type ISA0 16 Schmitt Input (GPIOA9) State During Reset Input, pull-up enabled Schmitt Input/ Output Signal Description ISA0 — This input current status pin is used for top/bottom pulse width correction in complementary channel operation for PWMA. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is ISA0.
Table 2-2 Signal and Package Information for the 64-Pin LQFP State During Reset Signal Name Pin No. Type VREFP 37 Input/ Output VREFMID 36 Analog Input/ VREFP, VREFMID & VREFN — Internal pins for voltage reference which Output are brought off-chip so that they can be bypassed. Connect to a 0.1μF ceramic low ESR capacitor VREFN 35 VREFLO 38 Schmitt Input Analog Input VREFLO — Analog Reference Voltage Low. This should normally be connected to a low-noise VSS.
Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name Pin No. Type State During Reset TC0 1 Schmitt Input/ Output Input, pull-up enabled (TXD0) Input (GPIOC6) Schmitt Input/ Output Signal Description TC0 — Timer C, Channel 0 Transmit Data — SCI0 transmit data output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC0.
Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. 3.2 External Clock Operation The system clock can be derived from an external crystal, ceramic resonator, or an external system clock signal.
Use of On-Chip Relaxation Oscillator Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 3 Terminal 2 Terminal EXTAL XTAL Rz CL1 EXTAL XTAL Rz CL2 Sample External Ceramic Resonator Parameters: Rz = 750 KΩ CLKMODE = 0 C1 C2 Figure 3-2 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a crystal resonator is used. The reset condition on the OCCS_COHL bit is 0.
to increase or decrease capacitance. Upon power-up, the default value of this trim is 512 units. Each unit added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the desired frequency accuracy is achieved. The internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash information block and loaded to the FMOPT1 register at reset.
Registers 3.5 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions with the internal Relaxation Oscillator, since the 56F8323 and 56F8123 contain this oscillator. Part 4 Memory Map 4.1 Introduction The 56F8323 and 56F8123 devices are 16-bit motor-control chips based on the 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program.
Note: Program RAM is NOT available on the 56F8123 device. Table 4-2 Program Memory Map at Reset Begin/End Address Memory Allocation P: $1F FFFF P: $03 0000 RESERVED P: $02 FFFF P: $02 F800 On-Chip Program RAM 4KB P: $02 F7FF P: $02 1000 RESERVED P: $02 0FFF P: $02 0000 Boot Flash 8KB Cop Reset Address = $02 0002 Boot Location = $02 0000 P: $01 FFFF P: $00 4000 RESERVED P: $00 3FFF P: $00 0000 Internal Program Flash 32KB 4.
Interrupt Vector Table Table 4-3 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function core 4 3 P:$08 HW Stack Overflow core 5 3 P:$0A Misaligned Long Word Access core 6 1-3 P:$0C OnCE Step Counter core 7 1-3 P:$0E OnCE Breakpoint Unit 0 Reserved core 9 1-3 P:$12 OnCE Trace Buffer core 10 1-3 P:$14 OnCE Transmit Register Empty core 11 1-3 P:$16 OnCE Receive Register Full Reserved core 14 2 P:$
Table 4-3 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function SCI1 45 0-2 P:$5A SCI 1 Receiver Error SCI1 46 0-2 P:$5C SCI 1 Receiver Full Reserved DEC0 49 0-2 P:$62 Quadrature Decoder #0 Home Switch or Watchdog DEC0 50 0-2 P:$64 Quadrature Decoder #0 INDEX Pulse Reserved TMRC 56 0-2 P:$70 Timer C Channel 0 TMRC 57 0-2 P:$72 Timer C Channel 1 TMRC 58 0-2 P:$74 Timer C Channel 2 TMRC 59 0-2 P:
Data Map 4.4 Data Map Note: Data Flash is NOT available on the 56F8122 device. Table 4-4 Data Memory Map1 Begin/End Address Memory Allocation X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 RESERVED X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 2000 RESERVED X:$00 1FFF X:$00 1000 On-Chip Data Flash 8KB X:$00 0FFF X:$00 0000 On-Chip Data RAM 8KB2 1. All addresses are 16-bit Word addresses. 2.
Data Memory Program Memory BOOT_FLASH_START + $0FFF FM_BASE + $14 8KB Boot BOOT_FLASH_START = $02_0000 FM_BASE + $00 Reserved Banked Registers Unbanked Registers DATA_FLASH_START + $0FFF 8KB DATA_FLASH_START + $0000 Configure Field FM_PROG_MEM_TOP = $00_3FFF Block 0 Odd Block 0 Even Note: Data Flash is NOT available in the 56F8123 device. ...
EOnCE Memory Map 4.
4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-7 summarizes base addresses for the set of peripherals on the 56F8323 and 56F8123 devices. Peripherals are listed in order of the base address.
Peripheral Memory Mapped Registers Table 4-8 Quad Timer A Registers Address Map (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CMP1 $0 Compare Register 1 TMRA0_CMP2 $1 Compare Register 2 TMRA0_CAP $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCR $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparato
Table 4-8 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_COMSCR $2A Comparator Status and Control Register Reserved TMRA3_CMP1 $30 Compare Register 1 TMRA3_CMP2 $31 Compare Register 2 TMRA3_CAP $32 Capture Register TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36 Control Register TMRA3_SCR $37 Sta
Peripheral Memory Mapped Registers Table 4-9 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC1_HOLD $14 Hold Register TMRC1_CNTR $15 Counter Register TMRC1_CTRL $16 Control Register TMRC1_SCR $17 Status and Control Register TMRC1_CMPLD1 $18 Comparator Load Register 1 TMRC1_CMPLD2 $19 Comparator Load Register 2 TMRC1_COMSCR $1A Comparator Status and Control Register Reserved TMRC2_CMP1 $20 Compare Regist
Table 4-10 Pulse Width Modulator A Registers Address Map (PWMA_BASE = $00 F140) PWM is NOT available in the 56F8123 device Register Acronym Address Offset Register Description PWMA_PMCTRL $0 Control Register PWMA_PMFCTRL $1 Fault Control Register PWMA_PMFSA $2 Fault Status Acknowledge Register PWMA_PMOUT $3 Output Control Register PWMA_PMCNT $4 Counter Register PWMA_PWMCM $5 Counter Modulo Register PWMA_PWMVAL0 $6 Value Register 0 PWMA_PWMVAL1 $7 Value Register 1 PWMA_PWMVAL2 $8
Peripheral Memory Mapped Registers Table 4-11 Quadrature Decoder 0 Registers Address Map (Continued) (DEC0_BASE = $00 F180) Quadrature Decoder is NOT available in the 56F8123 device Register Acronym Address Offset Register Description DEC0_UPOSH $9 Upper Position Hold Register DEC0_LPOSH $A Lower Position Hold Register DEC0_UIR $B Upper Initialization Register DEC0_LIR $C Lower Initialization Register DEC0_IMR $D Input Monitor Register Table 4-12 Interrupt Control Registers Address Map (I
Table 4-13 Analog-to-Digital Converter Registers Address Map (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR1 $0 Control Register 1 ADCA_CR2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Crossing Status Register ADCA_RSLT 0 $9
Peripheral Memory Mapped Registers Table 4-13 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_OFS 0 $21 Offset Register 0 ADCA_OFS 1 $22 Offset Register 1 ADCA_OFS 2 $23 Offset Register 2 ADCA_OFS 3 $24 Offset Register 3 ADCA_OFS 4 $25 Offset Register 4 ADCA_OFS 5 $26 Offset Register 5 ADCA_OFS 6 $27 Offset Register 6 ADCA_OFS 7 $28 Offset Register 7 ADCA_POWER $29 Power Control Regis
Table 4-17 Serial Peripheral Interface 0 Registers Address Map (SPI0_BASE = $00 F2A0) Register Acronym Address Offset Register Description SPI0_SPSCR $0 Status and Control Register SPI0_SPDSR $1 Data Size Register SPI0_SPDRR $2 Data Receive Register SPI0_SPDTR $3 Data Transmitter Register Table 4-18 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00 F2B0) Register Acronym Address Offset Register Description SPI1_SPSCR $0 Status and Control Register SPI1_SPDSR $1 Data
Peripheral Memory Mapped Registers Table 4-21 GPIOA Registers Address Map (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PUR $0 Pull-up Enable Register 0 x 0FFF GPIOA_DR $1 Data Register 0 x 0000 GPIOA_DDR $2 Data Direction Register 0 x 0000 GPIOA_PER $3 Peripheral Enable Register 0 x 0FFF GPIOA_IAR $4 Interrupt Assert Register 0 x 0000 GPIOA_IENR $5 Interrupt Enable Register 0 x 0000 GPIOA_IPOLR $6 Interrupt Polarity Register 0
Table 4-23 GPIOC Registers Address Map (GPIOC_BASE = $00 F310) Register Acronym Address Offset Register Description Reset Value GPIOC_PUR $0 Pull-up Enable Register 0 x 007C GPIOC_DR $1 Data Register 0 x 0000 GPIOC_DDR $2 Data Direction Register 0 x 0000 GPIOC_PER $3 Peripheral Enable Register 0 x 007F GPIOC_IAR $4 Interrupt Assert Register 0 x 0000 GPIOC_IENR $5 Interrupt Enable Register 0 x 0000 GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOC_IPR $7 Interrupt Pe
Peripheral Memory Mapped Registers Table 4-25 Power Supervisor Registers Address Map (LVI_BASE = $00 F360) Register Acronym Address Offset Register Description LVI_CONTROL $0 Control Register LVI_STATUS $1 Status Register Table 4-26 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FMCLKD $0 Clock Divider Register FMMCR $1 Module Control Register Reserved FMSECH $3 Security High Half Register FMSECL $4 Security Low Half Regis
Table 4-27 FlexCAN Registers Address Map (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym FCMCR Address Offset $0 Register Description Module Configuration Register Reserved FCCTL0 $3 Control Register 0 Register FCCTL1 $4 Control Register 1 Register FCTMR $5 Free-Running Timer Register FCMAXMB $6 Maximum Message Buffer Configuration Register Reserved FCRXGMASK_H $8 Receive Global Mask High Register FCRXGMASK_L $9 Receive Global Mask Low Register FCRX1
Peripheral Memory Mapped Registers Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym Address Offset Register Description FCMB1_DATA $4B Message Buffer 1 Data Register FCMB1_DATA $4C Message Buffer 1 Data Register FCMB1_DATA $4D Message Buffer 1 Data Register FCMB1_DATA $4E Message Buffer 1 Data Register Reserved FCMB2_CONTROL $50 Message Buffer 2 Control / Status Register FCMB2_ID_HIGH $51 Message Bu
Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym Address Offset Register Description FCMB5_DATA $6C Message Buffer 5 Data Register FCMB5_DATA $6D Message Buffer 5 Data Register FCMB5_DATA $6E Message Buffer 5 Data Register Reserved FCMB6_CONTROL $70 Message Buffer 6 Control / Status Register FCMB6_ID_HIGH $71 Message Buffer 6 ID High Register FCMB6_ID_LOW $72 Message Buffer 6 ID Low Register FCMB6_D
Peripheral Memory Mapped Registers Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym Address Offset Register Description FCMB9_DATA $8D Message Buffer 9 Data Register FCMB9_DATA $8E Message Buffer 9 Data Register Reserved FCMB10_CONTROL $90 Message Buffer 10 Control / Status Register FCMB10_ID_HIGH $91 Message Buffer 10 ID High Register FCMB10_ID_LOW $92 Message Buffer 10 ID Low Register FCMB10_DATA $
Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym FCMB13_DATA Address Offset $AE Register Description Message Buffer 13 Data Register Reserved FCMB14_CONTROL $B0 Message Buffer 14 Control / Status Register FCMB14_ID_HIGH $B1 Message Buffer 14 ID High Register FCMB14_ID_LOW $B2 Message Buffer 14 ID Low Register FCMB14_DATA $B3 Message Buffer 14 Data Register FCMB14_DATA $B4 Message Buffer 14 Data Register
Introduction Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.
Table 5-2. Interrupt Priority Encoding Current Interrupt Priority Level IPIC_LEVEL[1:0]1 Required Nested Exception Priority 00 No Interrupt or SWILP Priorities 0, 1, 2, 3 01 Priority 0 Priorities 1, 2, 3 10 Priority 1 Priorities 2, 3 11 Priorities 2 or 3 Priority 3 1. See IPIC field definition in Section 5.6.30.2 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does.
Block Diagram 5.4 Block Diagram any0 Priority Level INT1 Level 0 82 -> 7 Priority Encoder 2 -> 4 Decode 7 INT VAB CONTROL any3 Level 3 IACK SR[9:8] Priority Level INT82 IPIC 82 -> 7 Priority Encoder 7 PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default.
5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.
Register Descriptions Add.
5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 15 14 Read 0 0 13 12 BKPT_U0 IPL 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STPCNT IPL Write RESET 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.
Register Descriptions 5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.
5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.
Register Descriptions 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 Reserved—Bits 5–2 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.3.
5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.4 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.
5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.6.3 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.4 Reserved—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.6.
5.6.7 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 Read 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRC0 IPL Write RESET 0 0 3 2 DEC0_XIRQ IPL 0 0 1 0 DEC0_HIRQ IPL 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.8 Interrupt Priority Register 7 (IPR7) Base + $7 15 14 Read 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 TMRA0 IPL 5 4 TMRC3 IPL 3 2 TMRC2 IPL 1 0 TMRC1 IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.9.3 Reserved—Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0 TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.
5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA 1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.10.4 Reserved—Bits 9–8 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.
5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)— Bits 12–0 The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are determined based upon the highest-priority interrupt; see Part 5.3.1 for details. 5.6.
Register Descriptions 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $D 15 14 13 12 11 10 9 8 7 6 5 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 2 1 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH Write RESET 3 0 0 0 0 0 Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.14.
5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1) Base + $F 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS LOW Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 1.
Register Descriptions 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.19 IRQ Pending 1 Register (IRQP1) $Base + $12 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [32:17] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-21 IRQ Pending 1 Register (IRQP1) 5.6.19.
5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers two through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.22 IRQ Pending 4 Register (IRQP4) Base + $15 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [80:65] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-24 IRQ Pending 4 Register (IRQP4) 5.6.22.
Register Descriptions 5.6.24 Reserved—Base + 17 5.6.25 Reserved—Base + 18 5.6.26 Reserved—Base + 19 5.6.27 Reserved—Base + 1A 5.6.28 Reserved—Base + 1B 5.6.29 Reserved—Base + 1C 5.6.30 ITCN Control Register (ICTL) Base + $1D 15 Read INT 14 13 12 11 10 IPIC 9 8 7 6 5 VAB 4 3 2 1 0 1 0 IRQA STATE 0 IRQA EDG 1 1 1 0 0 INT_DIS Write RESET 0 0 0 1 0 0 0 0 0 0 0 Figure 5-26 ITCN Control Register (ICTL) 5.6.30.
5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. • • 0 = Normal operation (default) 1 = All interrupts disabled 5.6.30.5 Reserved—Bit 4 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.30.6 Reserved—Bit 3 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.30.
Introduction Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features.
6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — Total Reset Mode – 56800E Core and all peripherals are reset — Core-Only Reset Mode – 56800E Core in reset, peripherals are active – This mode is required to provide the on-chip Flash interface module time to load data from Flash into FM registers.
Register Descriptions 6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00F350) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CONTROL Control Register 6.5.1 Base + $1 SIM_RSTSTS Reset Status Register 6.5.2 Base + $2 SIM_SCR0 Software Control Register 0 6.5.3 Base + $3 SIM_SCR1 Software Control Register 1 6.5.3 Base + $4 SIM_SCR2 Software Control Register 2 6.5.3 Base + $5 SIM_SCR3 Software Control Register 3 6.5.
Add.
Register Descriptions 6.5.1.2 • • OnCE Enable (ONCE EBL)—Bit 5 0 = OnCE clock to 56800E core enabled when core TAP is enabled 1 = OnCE clock to 56800E core is always enabled 6.5.1.3 Software Reset (SW RST)—Bit 4 Writing 1 to this field will cause the part to reset. 6.5.1.
6.5.2.3 COP Reset (COPR)—Bit 4 When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.4 External Reset (EXTR)—Bit 3 If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software.
Register Descriptions Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 Write RESET Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $001D.
6.5.6.3 IRQ—Bit 10 This bit controls the pull-up resistors on the IRQA pin. 6.5.6.4 Reserved—Bits 9–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.5 JTAG—Bit 3 This bit controls the pull-up resistors on the TRST, TMS, and TDI pins. 6.5.6.6 Reserved—Bits 2–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.
Register Descriptions 6.5.7.4 • • 0 = Peripheral output function of GPIOB[5] is defined to be INDEX0 1 = Peripheral output function of GPIOB[5] is defined to be SYS_CLK 6.5.7.5 • • HOME0 (HOME)—Bit 6 0 = Peripheral output function of GPIOB[4] is defined to be HOME0 1 = Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see Figure 3-4) 6.5.7.
GPIOX_PER Register 0 GPIO Controlled I/O Pad Control 1 SIM_GPS Register 0 Quad Timer Controlled 1 SCI Controlled Figure 6-10 Overall Control of Pads Using SIM_GPS Control Base + $B 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 C6 C5 B1 B0 A5 A4 A3 A2 0 0 0 0 0 0 0 0 Write RESET 0 0 0 0 0 0 0 0 Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–8 This bit field is reserved or not implemented.
Register Descriptions 6.5.8.5 GPIOB0 (B0)—Bit 4 This bit selects the alternate function for GPIOB0. • • 0 = SS0 (default) 1 = TXD1 6.5.8.6 GPIOA5 (A5)—Bit 3 This bit selects the alternate function for GPIOA5. • • 0 = PWMA5 1 = SCLK1 6.5.8.7 GPIOA4 (A4)—Bit 2 This bit selects the alternate function for GPIOA4. • • 0 = PWMA4 1 = MOS1 6.5.8.8 GPIOA3 (A3)—Bit 1 This bit selects the alternate function for GPIOA3. • • 0 = PWMA3 1 = MISO1 6.5.8.
6.5.9.2 Analog-to-Digital Converter A Enable (ADCA)—Bit 13 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.3 FlexCAN Enable (CAN)—Bit 12 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.4 Reserved—Bit 11 This bit field is reserved or not implemented.
Register Descriptions 6.5.9.11 Serial Communications Interface 0 Enable (SCI0)—Bit 4 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
“Hard Coded” Address Portion Instruction Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them.
Clock Generation Overview 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz.
6.8 Stop and Wait Mode Disable Function Permanent Disable D Q D-FLOP C Reprogrammable Disable D 56800E STOP_DIS Q D-FLOP Clock Select C R Reset Note: Wait disable circuit is similar Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this.
Operation with Security Enabled Part 7 Security Features The 56F8323/56F8123 offer security features intended to prevent unauthorized users from reading the contents of the Flash memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array. However, part of the security must lie with the user’s code.
7.2.3 Flash Lockout Recovery If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration (.cfg) files.
Flash Access Blocking Mechanisms EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8=FM_CLKDIV[6]=0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.
Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F8300 Peripheral User Manual. 8.2 Configuration There are three GPIO ports defined on the 56F8323/56F8123. The width of each port and the associated peripheral function is shown in Table 8-1 and Table 8-2.
Configuration Table 8-3 GPIO External Signals Map Peripheral Function GPIO Function Package Pin Notes GPIOA0 PWMA0 3 PWM is NOT available in 56F8123 GPIOA1 PWMA1 4 PWM is NOT available in 56F8123 GPIOA2 PWMA2 / SSI 7 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8123 GPIOA3 PWMA3 / MISO1 8 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8123 GPIOA4 PWMA4 / MOSI1
Table 8-3 GPIO External Signals Map (Continued) GPIO Function Peripheral Function Package Pin Notes GPIOB7 PHASEA0 / TA0 52 Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Quad Decoder is NOT available in 56F8123 GPIOC0 EXTAL 46 Pull-ups default to disabled GPIOC1 XTAL 47 Pull-ups default to disabled GPIOC2 CAN_RX 61 CAN is NOT available in 56F8123 GPIOC3 CAN_TX 62 CAN is NOT available in 56F8123 GPIOC4 TC3 63 GPIOC5 TC1 / RXD0 64 SIM register SIM_
General Characteristics Part 10 Specifications 10.1 General Characteristics The 56F8323/56F8123 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.
Note: The 56F8123 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8123 device. Table 10-1 Absolute Maximum Ratings (VSS = VSSA_ADC = 0) Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less than or equal to VDDA_ADC VDDA_OSC_PLL Min Max Unit - 0.3 4.0 V - 0.3 4.0 V - 0.3 4.0 V VDD_CORE OCR_DIS is High - 0.3 3.
General Characteristics Table 10-2 56F8323/56F8123 ElectroStatic Discharge (ESD) Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Change Device Model (CDM) 500 — — V Table 10-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 64-pin LQFP Junction to ambient Natural Convection Junction to ambient (@1m/sec) RθJA 41 °C/W 2 RθJMA 34 °C/W 2 Junction to ambient Natural Convec
Note: The 56F8123 device is guaranteed to 40MHz and specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8123 device. Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic Supply voltage ADC Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less Min Typ Max Unit 3 3.3 3.6 V 3 3.3 3.6 V 3 3.3 3.6 V 2.25 2.5 2.
DC Electrical Characteristics 10.2 DC Electrical Characteristics Note: The 56F8123 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8123 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH = IOHmax Output Low Voltage VOL — — 0.
Table 10-6 Power-On Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point Rising1 PORR — — — V POR Trip Point Falling PORF 1.75 1.8 1.9 V LVI, 2.5V Supply, trip point2 VEI2.5 — 2.14 — V LVI, 3.3V supply, trip point3 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. Both VEI2.5 and VEI3.3 thresholds must be met for POR to be released on power-up. 2. When VDD_CORE drops below VEI2.5, an interrupt is generated. 3.
DC Electrical Characteristics Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) Mode RUN1_MAC IDD_Core IDD_IO1 IDD_ADC IDD_OSC_PLL 110mA 13μA 25mA 2.5mA Test Conditions • 60MHz Device Clock • All peripheral clocks are enabled • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 55mA 13μA 35μA 2.
Table 10-9. Regulator Parameters (Continued) Characteristic Symbol Min Typical Max Unit Short Circuit Current (output shorted to ground) Iss — — 700 mA Bias Current I bias — 5.8 7 mA Power-down Current Ipd — 0 2 μA Short-Circuit Tolerance (output shorted to ground) TRSC — — 30 minutes Table 10-10. PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start-up time TPS 0.3 0.5 10 ms Resonator Start-up time TRS 0.1 0.
AC Electrical Characteristics Table 10-11 Temperature Sense Parametrics (Continued) Characteristics Symbol Min Typical Max Unit Supply Current - OFF IDD-OFF — — 10 μA Supply Current - ON IDD-ON — — 250 μA Accuracy3,1 from -40°C to 150°C Using VTS = mT + VTS0 TACC -6.7 0 6.7 °C Resolution4, 5,1 RES — 0.104 — °C / bit 1. Includes the ADC conversion of the analog Temperature Sense voltage. 2.
Data2 Valid Data1 Valid Data1 Data3 Valid Data2 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 10-2 Signal States 10.4 Flash Memory Characteristics Table 10-12 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time 1 Tprog 20 — — μs Erase time2 Terase 20 — — ms Tme 100 — — ms Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for details.
Phase Locked Loop Timing VIH External Clock 90% 50% 10% 90% 50% 10% tfall tPW tPW VIL trise Note: The midpoint is VIL + (VIH – VIL)/2. Figure 10-3 External Clock Timing 10.6 Phase Locked Loop Timing Table 10-14 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 8.
Table 10-15 Crystal Oscillator Parameters (Continued) Characteristic Symbol Min Typ Max Unit Resonator Min-Max Period Variation TRP — — 300 ps Bias Current, high-drive mode IBIASH — 250 290 μA Bias Current, low-drive mode IBIASL — 80 110 μA Quiescent Current, power-down mode IPD — 0 1 μA Table 10-16 Relaxation Oscillator Parameters Characteristic Note: Min Typ Max Units Center Frequency — 8 — MHz Minimum Tuning Step Size (See Note) — 82 — ps Maximum Tuning Step
Reset, Stop, Wait, Mode Select, and Interrupt Timing 8.2 Typical Response 8.1 Frequency in MHz 8.0 7.9 7.8 7.7 7.6 7.5 - 30 - 50 - 10 + 10 + 30 + 50 + 70 + 90 + 110 + 130 + 150 Temperature Figure 10-4 Frequency versus Temperature 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All address and data buses described here are internal.
RESET tRA tRAZ tRDA PAB PDB First Fetch Figure 10-5 Asynchronous Reset Timing IRQA tIRW Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive) PAB First Interrupt Instruction Execution IRQA tIDM a) First Interrupt Instruction Execution General Purpose I/O Pin IRQA tIG b) General Purpose I/O Figure 10-7 External Level-Sensitive Interrupt Timing IRQA tIW tIF PAB First Instruction Fetch Not IRQA Interrupt Vector Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timin
Serial Peripheral Interface (SPI) Timing 10.
1 SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tR tF Figure 10-9 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in Bits 14–1 tDI tDV(ref) MOSI (Output) tDH Master
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) tD tF Slave MSB out Bits 14–1 tDS tDV Slave LSB o
10.10 Quad Timer Timing Table 10-19 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-13 Timer input high / low period PINHL 1T + 3 — ns 10-13 Timer output period POUT 1T - 3 — ns 10-13 POUTHL 0.5T - 3 — ns 10-13 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
Serial Communication Interface (SCI) Timing PPH PPH PPH PPH Phase A (Input) PHL PIN PHL Phase B PHL (Input) PIN PHL Figure 10-14 Quadrature Decoder Timing 10.12 Serial Communication Interface (SCI) Timing Table 10-21 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-15 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-16 Baud Rate2 1. Parameters listed are guaranteed by design. 2.
10.13 Controller Area Network (CAN) Timing Note: The CAN is NOT available in the 56F8123 device. Table 10-22 CAN Timing1 Characteristic Baud Rate Bus Wake-up detection Symbol Min Max Unit See Figure BRCAN — 1 Mbps — TWAKEUP TIPBUS — μs 10-17 1. Parameters listed are guaranteed by design MSCAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-17 Bus Wakeup Detection 10.
JTAG Timing 1/fOP tPW tPW VM VM VIH TCK (Input) VIL VM = VIL + (VIH – VIL)/2 Figure 10-18 Test Clock Input Timing Diagram TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 10-19 Test Access Port Timing Diagram TRST (Input) tTRST Figure 10-20 TRST Timing Diagram 56F8323 Technical Data, Rev.
10.15 Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters Characteristic Symbol Min Typ Max Unit VADIN VREFL — VREFH V Resolution RES 12 — 12 Bits Integral Non-Linearity1 INL — +/- 2.4 +/- 3.2 LSB2 Differential Non-Linearity DNL — +/- 0.7 < +1 LSB2 Input voltages Monotonicity GUARANTEED ADC internal clock fADIC 0.
Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit SINAD — 59.1 — db THD — 60.6 — db Spurious Free Dynamic Range SFDR — 61.1 — db Effective Number Of Bits8 ENOB — 9.6 — Bits Signal-to-noise plus distortion ratio Total Harmonic Distortion 1. INL measured from Vin = .1VREFH to Vin = .9VREFH 10% to 90% Input Signal Range 2. LSB = Least Significant Bit 3. ADC clock cycles 4.
Figure 10-21 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken on 15 parts: three each from four processing corner lots as well as three from one nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 45 data points shown above), for two input DC voltages: 0.60V and 2.70V.
Equivalent Circuit for ADC Inputs 10.16 Equivalent Circuit for ADC Inputs Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFLO)/2, while the other charges to the analog input voltage.
C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the IO cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero Y-intercept.
56F8323 Package and Pin-Out Information Part 11 Packaging 11.1 56F8323 Package and Pin-Out Information HOME0 INDEX0 PHASEB0 PHASEA0 TCK TMS TDI TDO VCAP1 TRST VDD_IO VSS CAN_RX CAN_TX TC3 TC1 This section contains package and pin-out information for the 56F8323. This device comes in a 64-pin Low-profile Quad Flat Pack (LQFP).
Table 11-1 56F8323 64-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8123 Package and Pin-Out Information 11.2 56F8123 Package and Pin-Out Information TA3 TA2 TA1 TA0 TCK TMS TDI TDO VCAP1 TRST VDD_IO VSS GPIOC2 GPIOC3 TC3 TC1 This section contains package and pin-out information for the 56F8123. This device comes in a 64-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the 64-pin LQFP, Figure 11-3 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the 64-pin LQFP case.
Table 11-2 56F8123 64-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8123 Package and Pin-Out Information 4X 4X 16 TIPS 0.2 H A-B D 0.2 C A-B D 64 A2 0.05 49 1 S (S) 48 2X R R1 q1 A 0.25 B q E E1 (L2) A1 3X E1/2 VIEW Y 16 E/2 VIEW AA 32 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE DATUM H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE DATUM C.
Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
Electrical Design Considerations The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
• • Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
Power Distribution and I/O Ring Implementation Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 13-1 Ordering Information Part Supply Voltage Pin Count Frequency (MHz) Temperature Range Order Number MC56F8323 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 64 60 -40° to + 105° C MC56F8323VFB60 MC56F8323 3.0–3.
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