Datasheet

Overview
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 9
Figure 1. 56800E Core Block Diagram
Figure 2 shows the peripherals and control blocks connected to the IP bus bridge. Refer to the system integration module (SIM)
section in the device’s reference manual for information about which signals are multiplexed with those of other peripherals.
Data
DSP56800E Core
Arithmetic
Logic Unit
(ALU)
XAB2
PAB
PDB
CDBW
CDBR
XDB2
Program
Memory
Data/
IP Bus
Interface
Bit-
Manipulation
Unit
N3
M01
Address
XAB1
Generation
Unit
(AGU)
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
FISR
LC
LC2
Instruction
Decoder
Interrupt
Unit
Looping
Unit
Program Control Unit
ALU1 ALU2
MAC and ALU
A1A2 A0
B1B2 B0
C1C2 C0
D1D2 D0
Y1
Y0
X0
Enhanced
JTAG TAP
R2
R3
R4
R5
SP
R0
R1
N
Y
Multi-Bit Shifter
OnCE™
Program
RAM