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Interrupt Vector Table

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3

Freescale Semiconductor 85

Appendix A

Interrupt Vector Table

Table 48 provides the MC56F825x/MC56F824x’s reset and interrupt priority structure, including on-chip peripherals. The table

is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of

an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced

before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority.

The location of the vector table is determined by the vector base address (VBA). See the device’s reference manual for details.

By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these cases,

the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR

instructions.

Table 48. Interrupt Vector Table Contents

Peripheral

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

Core P:0x00 Reserved for Reset Overlay

Core

P:0x02 Reserved for COP Reset Overlay

Core 2 3 P:0x04 Illegal Instruction

Core 3 3 P:0x06 SW Interrupt 3

Core 4 3 P:0x08 HW Stack Overflow

Core 5 3 P:0x0A Misaligned Long Word Access

Core 6 1 - 3 P:0x0C EOnCE Step Counter

Core 7 1 - 3 P:0x0E EOnCE Breakpoint Unit

Core 8 1 - 3 P:0x10 EOnCE Trace Buffer

Core 9 1 - 3 P:0x12 EOnCE Transmit Register Empty

Core 10 1 - 3 P:0x14 EOnCE Receive Register Full

Core 11 2 P:0x16 SW Interrupt 2

Core 12 1 P:0x18 SW Interrupt 1

Core 13 0 P:0x1A SW Interrupt 0

PS 14 1 - 3 P:0x1C Low-Voltage Interrupt

OCCS 15 1 - 3 P:0x1E Phase-Locked Loop Loss of Locks and Loss of Clock

TMRB3 16 0 - 2 P:0x20 Quad Timer B, Channel 3 Interrupt

TMRB2 17 0 - 2 P:0x22 Quad Timer B, Channel 2Interrupt

TMRB1 18 0 - 2 P:0x24 Quad Timer B, Channel 1Interrupt

TMRB0 19 0 - 2 P:0x26 Quad Timer B, Channel 0 Interrupt

ADCB_CC 20 0 - 2 P:0x28 ADCB Conversion Complete Interrupt

ADCA_CC 21 0 - 2 P:0x2A ADCA Conversion Complete Interrupt

ADC_Err 22 0 - 2 P:0x2C ADC Zero crossing, Low limit, and high limit interrupt

CAN 23 0 - 2 P:0x2E CAN Transmit Interrupt

CAN 24 0 - 2 P:0x30 CAN Receive Interrupt