Datasheet

Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 71
7.27 5-Bit Digital-to-Analog Converter (DAC) Parameters
7.28 HSCMP Specifications
7.29 Optimize Power Consumption
See Section 7.7, “Supply Current Characteristics,” for a list of I
DD
requirements for the MC56F825x/MC56F824x. This section
provides additional details for optimizing power consumption for a given application.
Power consumption is given by the following equation:
A, the internal [static] component, consists of the DC bias currents for the oscillator, leakage currents, PLL, and voltage
references. These sources operate independently of processor state or operating frequency.
1
No guaranteed specification within 5% of V
DDA
or V
SSA
2
LSB = 0.806 mV
Table 43. 5-Bit DAC Specifications
Parameter Symbol Min Typ Max Unit
Reference Inputs Vin V
DDA
— V
DDA
mV
Setup Delay t
PRGST
TBD TBD TBD ns
Step size V
STEP
3Vin/128 Vin/32 5Vin/128 V
Output Range V
DACOUT
Vin/32 — Vin ns
Table 44. HSCMP Specifications
Parameter Symbol Min Typ Max Unit
Analog input voltage V
AIN
V
SSA
– 0.01 — V
DDA
+ 0.01 V
Analog input offset voltage
1
1
Offset when the degree of hysteresis is set to its minimum value.
V
AIO
——40 mV
Analog comparator hysteresis
2
2
The range of hysteresis is based on simulation only. This range varies from part to part.
V
H
— 1 to 16 — mV
Propagation Delay, high speed mode (EN=1,
PMODE=1),
t
DHSN
3
3
Measured with an input waveform that switches 30 mV above and below the reference, to the CMPO output pin. V
DDA
>
V
LVI_WARNING
=> LVI_WARNING NOT ASSERTED.
— 70 140 ns
Propagation Delay, Low Speed Mode (EN=1,
PMODE=0),
t
AINIT
4
4
Measured with an input waveform that switches 30 mV above and below the reference, to the CMPO output pin. V
DDA
>
V
LVI_WARNING
=> LVI_WARNING NOT ASSERTED.
— 400 600 ns
Total power = A: internal [static] component
+B: internal [state-dependent] component
+C: internal [dynamic] component
+D: external [dynamic] component
+E: external [static] component