Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor70
2. Parasitic capacitance due to the chip bond pad, ESD protection devices, and signal routing: 2.04 pF
3. 8 pF noise damping capacitor
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time: C
gain
= 1.4 pF for x1 gain, 2.8 pF for x2 gain, and 5.6 pF for x4 gain.
5. S1 and S2 switch phases are non-overlapping and operate at the ADC clock frequency.
Figure 31. Equivalent Circuit for A/D Loading
7.26 Digital-to-Analog Converter (DAC) Parameters
Table 42. DAC Parameters
Parameter Conditions/Comments Symbol Min Typ Max Unit
DC Specifications
Resolution 12 — 12 bits
Settling time At output load
R
LD
= 3 KΩ
C
LD
= 400 pf
TBD — 2 µS
Power-up time Time from release of PWRDWN
signal until DACOUT signal is
valid
t
DAPU
— — 11 µS
Accuracy
Integral non-linearity
1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
INL — +/- 3 +/- 8.0
LSB
2
Differential non-linearity
1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
DNL — +/- 0.8 +/- 1.0
LSB
2
Monotonicity > 6 sigma monotonicity,
< 3.4 ppm non-monotonicity
guaranteed —
Offset error
1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
V
OFFSET
— +/- 25 +/- 40 mV
Gain error
1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
E
GAIN
— +/- .5 +/- 1.5 %
DAC Output
Output voltage range Within 40 mV of either V
REFLX
or
V
REFHX
V
OUT
V
REFLX
+0.04V
—V
REFHX
- 0.04V
V
AC Specifications
Signal-to-noise ratio SNR — TBD — dB
Spurious free dynamic
range
SFDR — TBD — dB
Effective number of bits ENOB — — — Bits
S1
S2