Datasheet

Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 69
7.25.1 Equivalent Circuit for ADC Inputs
Figure 31 illustrates the ADC input circuit during sample and hold. S1 and S2 are always opened/closed at non-overlapping
phases and operate at the ADC clock frequency. Equivalent input impedance, when the input is selected, is as follows:
(2 x k / ADCClockRate x C
gain
) + 100 ohms + 125 ohms Eqn. 1
where k =
• 1 for first sample
• 6 for subsequent samples
and C
gain
is as described in note 4 below.
1. Parasitic capacitance due to package, pin-to-pin, and pin-to-package base coupling: 1.8 pF
Input impedance
X
IN
—See Figure 31 —Ohms
AC Specifications
9
(gain of 1x, 2x, 4x and f
ADC
≤ 10 MHz)
4
Signal-to-noise ratio
SNR — 59 dB
Total Harmonic Distortion
THD — 64 dB
Spurious Free Dynamic Range
SFDR — 65 dB
Signal-to-noise plus distortion
SINAD — 59 dB
Effective Number Of Bits
ENOB — 9.5 Bits
1
All measurements were made at V
DD
= 3.3V, V
REFH
= 3.3V, and V
REFL
= ground
2
Includes power-up of ADC and V
REF
3
ADC clock cycles
4
Speed register setting must be 00 for ADC clock ≤ 5 MHz, 01 for 5 MHz < ADC clock ≤ 12 MHz, and 10 for ADC clock > 12 MHz
5
INL and DNL measured from V
IN
= V
REFL
to V
IN
= V
REFH
6
LSB = Least Significant Bit = 0.806 mV at x1 gain
7
Pin groups are detailed following Table 17.
8
The current that can be injected or sourced from an unselected ADC signal input without affecting the performance of the ADC
9
ADC PGA gain is x1
Table 41. ADC Parameters
1
(continued)
Parameter Symbol Min Typ Max Unit
1
2
3
Analog input
S1
S1
S2
C1
C1
S/H
C1: Single Ended Mode
2XC1: Differential Mode
(V
REFHx
- V
REFLx
) / 2
125-ohm ESD
resisto
r
S2
S1
S1
Channel Mux
equivalent resistance
100 ohms
C1: Single Ended Mode
2XC1: Differential Mode